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    Digital data processing system using unique ALU register files and micro-instruction stacks
    22.
    发明授权
    Digital data processing system using unique ALU register files and micro-instruction stacks 失效

    公开(公告)号：US4480306A

    公开(公告)日：1984-10-30

    申请号：US266425

    申请日：1981-05-22

    申请人： Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  John F. Pilat ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr. ,  Douglas M. Wells

    发明人： Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  John F. Pilat ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr. ,  Douglas M. Wells

    IPC分类号： G06F9/26 ,  G06F9/22

    CPC分类号： G06F9/26

    摘要： A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described with reference to the invention herein, identify locations of object information to be accessed by utlizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format. Arithmetic logic unit (ALU) means, also as particularly described with reference to the invention herein, include general register means having three vertically oriented parts for storing such respective fields. Such ALU means further include an ALU microinstruction stack means having at least one microinstruction stack frame for storing the state of execution of a microinstruction. A memory microinstruction stack is provided to store a plurality of microinstruction stack frames so that microinstruction stack frames can be transferred between the ALU and the memory microinstruction stacks. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.