公开(公告)号：US20110106741A1

公开(公告)日：2011-05-05

申请号：US12611968

申请日：2009-11-04

申请人： Monty M. Denneau ,  Daniel J. Friedman ,  Ralph Linsker ,  Mark B. Ritter

发明人： Monty M. Denneau ,  Daniel J. Friedman ,  Ralph Linsker ,  Mark B. Ritter

IPC分类号： G06F15/18 ,  G06N3/08

CPC分类号： H04L47/521

摘要： A system, method, and design structure for address-event-representation network simulation are provided. The system includes a hardware structure with a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes. To simulate each node, the hardware structure includes a source table configured to receive an input message and identify a weight associated with a source of the input message. The hardware structure also includes state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state. The hardware structure further includes a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. The hardware structure may further include learning logic configured to combine information about input messages and generated output signals, and to update weights.

摘要翻译： 提供了一种用于地址事件表示网络仿真的系统，方法和设计结构。 该系统包括硬件结构，其具有被配置为模拟多个互连节点的多个互连的处理模块。 为了模拟每个节点，硬件结构包括被配置为接收输入消息并且识别与输入消息的源相关联的权重的源表。 硬件结构还包括状态管理逻辑，其被配置为根据所识别的权重更新节点状态，并响应于更新的节点状态生成输出信号。 硬件结构进一步包括目标表，其被配置为响应于输出信号产生输出消息，识别目标以接收输出消息，并发送输出消息。 硬件结构还可以包括被配置为组合关于输入消息和生成的输出信号的信息并且更新权重的学习逻辑。

公开(公告)号：US20100214078A1

公开(公告)日：2010-08-26

申请号：US12779103

申请日：2010-05-13

申请人： Han Chen ,  Daniel J. Friedman ,  Paul A. Moskowitz

发明人： Han Chen ,  Daniel J. Friedman ,  Paul A. Moskowitz

IPC分类号： H04Q5/22

CPC分类号： G06K19/0723 ,  G06K19/0701 ,  G08B13/2417

摘要： A system and method are provided for modifying the effective reading range of an radio frequency identification tag. The tag, a chip-based tag, includes an antenna and a chip in communication with the antenna. The chip includes circuitry including field effect transistors that can modify the effective reading range of the tag by modifying characteristics of the tag including the modulation depth of the backscatter signal, the impedance characteristics of the tag front end electronics, the power consumption characteristics and the threshold power-on voltage of the tag. These characteristics are change either temporarily or permanently in response to commands communicated to the tag from a radio frequency identification reader.

摘要翻译： 提供了一种用于修改射频识别标签的有效读取范围的系统和方法。 标签是基于芯片的标签，包括与天线通信的天线和芯片。 芯片包括电路，其包括场效应晶体管，其可以通过修改标签的特性来修改标签的有效读取范围，包括反向散射信号的调制深度，标签前端电子器件的阻抗特性，功耗特性和阈值 标签的上电电压。 响应于从射频识别读取器传送给标签的命令，这些特征暂时或永久地改变。

公开(公告)号：US20100188158A1

公开(公告)日：2010-07-29

申请号：US12358736

申请日：2009-01-23

申请人： Herschel A. Ainspan ,  John F. Bulzacchelli ,  Zeynep Toprak Deniz ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  John F. Bulzacchelli ,  Zeynep Toprak Deniz ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/099

CPC分类号： H03L7/081 ,  H03L7/085 ,  H03L7/099

摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.

摘要翻译： 数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。 相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。 数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。

公开(公告)号：US07721134B2

公开(公告)日：2010-05-18

申请号：US11566576

申请日：2006-12-04

申请人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

发明人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

IPC分类号： H04L25/00 ,  H03D3/24

CPC分类号： G01R31/3171 ,  B82Y25/00 ,  G01R33/093

摘要： A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.

摘要翻译： 提出了一种用于在诊断测试期间确定接收机系统的眼图边缘参数的方法和系统。 接收机前端的电路包括一系列锁存器，XOR门和OR门，它们首先提供数据样本和边缘采样，即在（边沿）时钟的上升沿或下降沿采样的数据，其特征在于相位延迟相对 到数据采样时钟。 接收机还包括用于边缘时钟（边缘）与数据边缘的理想对准的优化电路。 该方法还提供了边缘时钟从理想/锁定位置向左和向右移相以屏蔽数据眼图，以便计算误码率（BER）值。 边缘时钟相对于数据采样时钟的位置决定了计算的BER的水平眼睛开度。

公开(公告)号：US20100013532A1

公开(公告)日：2010-01-21

申请号：US12173159

申请日：2008-07-15

申请人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/08

CPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/50

摘要： Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control.

摘要翻译： 提供了电路和方法，其中数字PLL电路中的DCO（数字控制振荡器）电路的微调控制通过在数字控制下对多路复用器电路进行抖动控制来实现，以选择性地输出具有变化的电压电平的多个模拟控制电压中的一个 输入到DCO的分数频率控制端口，以分数频率分辨率驱动DCO的调谐元件，并在模拟控制下实现DCO的连续微调。

公开(公告)号：US06404325B1

公开(公告)日：2002-06-11

申请号：US09330786

申请日：1999-06-11

申请人： Harley Kent Heinrich ,  Daniel J. Friedman

发明人： Harley Kent Heinrich ,  Daniel J. Friedman

IPC分类号： H04Q100

CPC分类号： G06K19/0712 ,  G06K19/0707 ,  G06K19/0723

摘要： The present invention assures the integrity of state information retained by a Radio Frequency Transponder during a loss of power. During the regular operation of the Transponder power is provided to a voltage-storing device powering an information retention mechanism of the Transponder. After the loss and reestablishing of power to the Transponder but before the Transponder is restarted, the voltage-storing device is checked to determine whether sufficient power is present in the information retention mechanism to retain information without corruption. If sufficient power is present, a signal to indicate that fact is communicated to the Transponder and the stored information is restored. The Transponder is then restarted.

摘要翻译： 本发明确保在功率损失期间由射频应答器保留的状态信息的完整性。 在应答器的正常操作期间，将功率提供给为应答器的信息保持机制供电的蓄电装置。 在应答器丢失并重新建立电源后，在应答器重新启动之前，检查蓄电装置，以确定信息保留机制中是否存在足够的电力以保留信息而不会发生损坏。 如果存在足够的功率，则指示该事实的信号被传送到应答器，并恢复存储的信息。 然后重新启动应答器。

公开(公告)号：US06239703B1

公开(公告)日：2001-05-29

申请号：US09300968

申请日：1999-04-28

申请人： Daniel J. Friedman ,  Paul A. Moskowitz ,  Michael J. Brady ,  Dah-Weih Duan ,  Harley K. Heinrich

发明人： Daniel J. Friedman ,  Paul A. Moskowitz ,  Michael J. Brady ,  Dah-Weih Duan ,  Harley K. Heinrich

IPC分类号： G08B1341

CPC分类号： H01L24/05 ,  G08B13/2431 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00011 ,  H01L2224/45099

摘要： A bonding pad for a semiconductor device is provided with a mechanical supportive structure substantially surrounding the pad. The mechanical supportive structure prevents cracking of passivation material over the pad when a lead is compression bonded to the pad.

摘要翻译： 用于半导体器件的接合焊盘设置有基本上围绕焊盘的机械支撑结构。 机械支撑结构防止当铅压接在衬垫上时钝化材料在焊盘上的破裂。

公开(公告)号：US6104291A

公开(公告)日：2000-08-15

申请号：US167026

申请日：1998-10-06

申请人： Luc Beauvillier ,  Michael John Brady ,  Dah-Weih Duan ,  Daniel J. Friedman ,  Paul Andrew Moskowitz ,  Philip Murphy

发明人： Luc Beauvillier ,  Michael John Brady ,  Dah-Weih Duan ,  Daniel J. Friedman ,  Paul Andrew Moskowitz ,  Philip Murphy

IPC分类号： G06K17/00 ,  G06K19/07 ,  G06K19/077 ,  G08B13/24 ,  G08B21/00

CPC分类号： G08B13/2408 ,  G06K19/0723 ,  G06K19/07749 ,  G06K7/0095 ,  G06K7/10079 ,  G08B13/2417 ,  G08B13/244 ,  G01R31/2822 ,  G06K2017/0041

摘要： The present invention provides a method and apparatus for testing RFID tags using wireless radio frequency (RF) communication. The method and apparatus allow RFID tags to be tested individually or in groups while they are in close proximity to each other (e.g., within the read range of the tag).

摘要翻译： 本发明提供一种使用无线射频（RF）通信来测试RFID标签的方法和装置。 该方法和装置允许RFID标签在它们彼此靠近的地方（例如，在标签的读取范围内）被单独或分组地测试。

公开(公告)号：US08704567B2

公开(公告)日：2014-04-22

申请号：US13611008

申请日：2012-09-12

申请人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/06

CPC分类号： H03L7/1072 ,  H03L7/087 ,  H03L7/089 ,  H03L7/093

摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

公开(公告)号：US08476945B2

公开(公告)日：2013-07-02

申请号：US13069653

申请日：2011-03-23

申请人： Danny Elad ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Danny Elad ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/06

CPC分类号： H03L7/06 ,  H03L2207/06

摘要： Phase profile generator systems and methods are disclosed. A system includes a signal generator, a target phase trajectory module, an error detector and a control loop filter. The signal generator is configured to generate an output signal. In addition, the target phase trajectory module is configured to track a target phase trajectory and determine a next adjustment of the output signal to conform the output signal to a portion of the target phase trajectory. Further, the error detector is configured to determine an error between the output signal and a current target phase trajectory value that precedes the portion of the target phase trajectory, where the determination of the error is independent of the next adjustment of the output signal. Moreover, the control loop filter is configured to control the signal generator in accordance with both the next adjustment and the error to generate a phase profile.

摘要翻译： 公开了相位轮廓发生器系统和方法。 系统包括信号发生器，目标相位轨迹模块，误差检测器和控制环路滤波器。 信号发生器被配置为产生输出信号。 另外，目标相位轨迹模块被配置为跟踪目标相位轨迹，并且确定输出信号的下一个调整以使输出信号符合目标相位轨迹的一部分。 此外，误差检测器被配置为确定输出信号和在目标相位轨迹的部分之前的当前目标相位轨迹值之间的误差，其中误差的确定与输出信号的下一个调整无关。 此外，控制环路滤波器被配置为根据下一个调整和误差来控制信号发生器以产生相位分布。