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公开(公告)号：US08570079B2
公开(公告)日：2013-10-29
申请号：US13226557
申请日：2011-09-07
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L2207/06
摘要： There is provided a method for reducing lock time in a phase locked loop. The method includes detecting a saturation condition on a path within the phase locked loop. The method further includes temporarily applying saturation compensation along the path when the saturation condition is detected.
摘要翻译： 提供了一种减少锁相环锁定时间的方法。 该方法包括检测锁相环内的路径上的饱和状态。 该方法还包括当检测到饱和条件时，沿路径暂时施加饱和补偿。
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22.发明授权Method and circuit for controlling clock frequency of an electronic circuit with noise mitigation 有权用于控制噪声减轻的电子电路的时钟频率的方法和电路公开(公告)号：US07863952B2
公开(公告)日：2011-01-04
申请号：US12023933
申请日：2008-01-31
IPC分类号： H03L7/06
CPC分类号： H03L7/1976 , H03L2207/50
摘要： A technique to mitigate noise spikes in an electronic circuit device such as an integrated circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneously large changes to the clock frequency are avoided by use of a frequency filter that is capable of generating frequency ramps having a linear slope which is used as a feedback signal in a digital phase-locked loop clock circuit in lieu of a discrete, stair-stepped feedback control signal.
摘要翻译： 一种减轻诸如集成电路的电子电路装置中的噪声尖峰的技术。 控制由电子电路使用的时钟信号的时钟频率，使得能够通过使用能够产生具有用作反馈信号的线性斜率的频率斜坡的频率滤波器来避免对时钟频率的瞬时大的改变 数字锁相环时钟电路代替离散的楼梯阶反馈控制信号。
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23.发明申请METHOD AND APPARATUS FOR LOW LATENCY PROPORTIONAL PATH IN A DIGITALLY CONTROLLED SYSTEM 有权用于数字控制系统中低延迟比例路径的方法和装置公开(公告)号：US20100017690A1
公开(公告)日：2010-01-21
申请号：US12175012
申请日：2008-07-17
CPC分类号： H03L7/10 , H03L7/093 , H03L7/099 , H03L2207/06
摘要： A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).
摘要翻译： 数字控制电路和方法包括耦合到比例路径的误差输入。 比例路径包括直接接收误差输入作为选择信号的选择器。 选择器从比例路径（其中比例控制权重被输入到数字控制振荡器（DCO））以外的位置接收比例控制权重。
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24.发明授权Methods and apparatus for clock synchronization and data recovery in a receiver 有权接收机中时钟同步和数据恢复的方法和装置公开(公告)号：US07602869B2
公开(公告)日：2009-10-13
申请号：US11193868
申请日：2005-07-29
申请人： Azita Emami-Neyestanak , Mounir Meghelli , Benjamin D. Parker , Sergey V. Rylov , Alexander V. Rylyakov , Jose A. Tierno
发明人： Azita Emami-Neyestanak , Mounir Meghelli , Benjamin D. Parker , Sergey V. Rylov , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point. Further, for a next sampling cycle, the first clock may be used to sweep through phase positions with respect to the set phase position of the second clock corresponding to the sampling point in the first sampling cycle such that a next sampling point may be determined.
摘要翻译： 公开了时钟同步和数据恢复技术。 例如，用于同步用于恢复接收到的数据的时钟的技术包括以下步骤/操作。 将第一时钟（例如，数据时钟）设置为在接收到的数据中的给定单位间隔内的第一相位位置的第一采样周期。 第二时钟（例如，扫描时钟）相对于第一相位位置扫过其它相位位置，从而确定从接收到的数据中的给定单位间隔到另一个单位间隔的转变。 基于与第二时钟相关联的相位位置处的测量来确定采样点。 将第二时钟设置为对应于采样点的相位位置，使得可以在该采样点恢复数据。 此外，对于下一采样周期，可以使用第一时钟相对于与第一采样周期中的采样点对应的第二时钟的设置相位位置扫描相位位置，使得可以确定下一采样点。
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25.发明授权Technique for efficiently managing both short-term and long-term frequency adjustments of an electronic circuit clock signal 失效用于有效管理电子电路时钟信号的短期和长期频率调整的技术公开(公告)号：US07579887B1
公开(公告)日：2009-08-25
申请号：US12024457
申请日：2008-02-01
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03L7/08 , H03L7/0991 , H03L2207/50
摘要： A control system for generating an electronic circuit clock signal that can optimize operating frequency margins by responding to short term effects by quickly varying the clock frequency and long term effects by finding an optimal frequency point. A sensor indicates frequency margins associated with safe use of the clock signal, and these frequency margins are input into a frequency compensator and used to determine whether the system is operating within acceptable margins, or alternatively to modify the operating clock frequency on a short-term basis in order to achieve acceptable operating margins. The requests for frequency adjustment by the frequency compensator are provided to a frequency filter, which combines such request with a maintained/accumulated history of previous short-term frequency requests that have previously been made in order to determine whether an update needs to be made to the target frequency to provide long-term frequency control.
摘要翻译： 一种用于产生电子电路时钟信号的控制系统，其可以通过通过找到最佳频率点快速改变时钟频率和长期效应来响应短期效应来优化工作频率裕度。 传感器表示与安全使用时钟信号相关的频率裕度，并且这些频率余量被输入到频率补偿器中，用于确定系统是否在可接受的裕度内运行，或者替代地在短时间内修改工作时钟频率 为了达到可接受的经营利润。 将频率补偿器进行频率调整的请求提供给频率滤波器，该频率滤波器将这样的请求与先前已经做出的以前的短期频率请求的维持/累积历史相结合，以便确定是否需要进行更新 目标频率提供长期频率控制。
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公开(公告)号：US08593226B2
公开(公告)日：2013-11-26
申请号：US13226650
申请日：2011-09-07
IPC分类号： H03F3/08
CPC分类号： H03F3/08
摘要： A circuit includes a transimpedance amplifier portion having a first input node and a second input node, and a feedback circuit portion comprising a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal.
摘要翻译： 一种电路包括具有第一输入节点和第二输入节点的跨阻放大器部分，以及反馈电路部分，包括具有连接到第一输入节点的漏极端子，源极端子和栅极端子的第一晶体管，第二晶体管 具有连接到第二输入节点的漏极端子，源极端子和栅极端子，以及具有连接到第一晶体管的源极端子和第二端子的源极端子的漏极端子的第三晶体管。
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公开(公告)号：US07847641B2
公开(公告)日：2010-12-07
申请号：US12142123
申请日：2008-06-19
IPC分类号： H03L7/065
CPC分类号： H03L7/091 , H03L7/093 , H03L2207/50
摘要： Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.
摘要翻译： 公开了一种数字相位频率检测器和操作数字相位频率检测器的方法。 检测器包括输入电路，输出电路和复位电路。 在使用中，输入电路在多个周期期间接收第一和第二输入信号，并且在给定的一个周期期间，根据第一和第二输入信号中的哪一个首先被接收来产生第一中间信号或第二中间信号 在给定一个所述周期期间。 输出电路接收这些中间信号，并且在所述一个周期期间输出第一输出信号或第二输出信号，取决于在所述一个周期期间由输出电路接收到哪个中间信号。 复位电路在限定的条件下向输入电路施加复位信号以开始所述多个周期中的新的周期。
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28.发明申请公开(公告)号：US20090195275A1
公开(公告)日：2009-08-06
申请号：US12024457
申请日：2008-02-01
IPC分类号： H03L7/085
CPC分类号： H03L7/093 , H03L7/08 , H03L7/0991 , H03L2207/50
摘要： A control system for generating an electronic circuit clock signal that can optimize operating frequency margins by responding to short term effects by quickly varying the clock frequency and long term effects by finding an optimal frequency point. A sensor indicates frequency margins associated with safe use of the clock signal, and these frequency margins are input into a frequency compensator and used to determine whether the system is operating within acceptable margins, or alternatively to modify the operating clock frequency on a short-term basis in order to achieve acceptable operating margins. The requests for frequency adjustment by the frequency compensator are provided to a frequency filter, which combines such request with a maintained/accumulated history of previous short-term frequency requests that have previously been made in order to determine whether an update needs to be made to the target frequency to provide long-term frequency control.
摘要翻译： 一种用于产生电子电路时钟信号的控制系统，其可以通过通过找到最佳频率点快速改变时钟频率和长期效应来响应短期效应来优化工作频率裕度。 传感器表示与安全使用时钟信号相关的频率裕度，并且这些频率余量被输入到频率补偿器中，用于确定系统是否在可接受的裕度内运行，或者替代地在短时间内修改工作时钟频率 为了达到可接受的经营利润。 将频率补偿器进行频率调整的请求提供给频率滤波器，该频率滤波器将这样的请求与先前已经做出的以前的短期频率请求的维持/累积历史相结合，以便确定是否需要进行更新 目标频率提供长期频率控制。
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公开(公告)号：US07498894B1
公开(公告)日：2009-03-03
申请号：US12204622
申请日：2008-09-04
CPC分类号： H03B5/1243 , H03B2200/005
摘要： A system in one embodiment includes a voltage controlled oscillator; at least two varactors coupled to a tank node, each of the varactors being of a different physical size, the tank node being coupled to the voltage controlled oscillator; and switches for selectively turning the varactors on and off, wherein switching a first of the varactors from off to on and a second of the varactors from on to off creates a capacitance step of less than about 10 fF thereby tuning the voltage controlled oscillator from a first state to a second state.
摘要翻译： 一个实施例中的系统包括压控振荡器; 耦合到罐节点的至少两个变容二极管，每个变容二极管具有不同的物理尺寸，所述罐节点耦合到所述压控振荡器; 以及用于选择性地打开和关闭变容二极管的开关，其中将变容二极管中的第一个从断开切换到导通，以及变容二极管中的第二个从导通到断开产生小于约10fF的电容步长，从而将压控振荡器从 第一状态到第二状态。
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公开(公告)号：US20080246545A1
公开(公告)日：2008-10-09
申请号：US12142123
申请日：2008-06-19
CPC分类号： H03L7/091 , H03L7/093 , H03L2207/50
摘要： Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.
摘要翻译： 公开了一种数字相位频率检测器和操作数字相位频率检测器的方法。 检测器包括输入电路，输出电路和复位电路。 在使用中，输入电路在多个周期期间接收第一和第二输入信号，并且在给定的一个周期期间，根据第一和第二输入信号中的哪一个首先被接收来产生第一中间信号或第二中间信号 在给定一个所述周期期间。 输出电路接收这些中间信号，并且在所述一个周期期间输出第一输出信号或第二输出信号，取决于在所述一个周期期间由输出电路接收到哪个中间信号。 复位电路在限定的条件下向输入电路施加复位信号以开始所述多个周期中的新的周期。
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