公开(公告)号：US09128771B1

公开(公告)日：2015-09-08

申请号：US12633702

申请日：2009-12-08

Applicant: Gaurav Garg ,  David T. Hass

Inventor： Gaurav Garg ,  David T. Hass

IPC: G06F9/46 ,  G06F15/16 ,  G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5027 ,  G06F9/505 ,  G06F9/5088 ,  G06F9/546 ,  G06F2209/548

Abstract: A system, method, and computer program product are provided for sending a message from a first queue to a second queue associated with a receiver agent in response to a request. In operation, a message is sent from a sender agent to a first queue. Additionally, a request is received at the first queue from a receiver agent. Furthermore, the message is sent from the first queue to a second queue associated with the receiver agent, in response to the request.

Abstract translation: 提供了系统，方法和计算机程序产品，用于响应于请求将消息从第一队列发送到与接收方代理相关联的第二队列。 在操作中，消息从发送方代理发送到第一个队列。 另外，从接收方代理处接收到第一个队列的请求。 此外，响应于该请求，将消息从第一队列发送到与接收方代理相关联的第二队列。

公开(公告)号：US08725919B1

公开(公告)日：2014-05-13

申请号：US13164319

申请日：2011-06-20

Applicant: Julianne J. Zhu ,  David T. Hass

Inventor： Julianne J. Zhu ,  David T. Hass

IPC: G06F13/00

CPC classification number: G06F9/4411 ,  G06F13/102 ,  G06F2213/0026 ,  G06F2213/0058

Abstract: Disclosed is an approach for configuring devices for a multiprocessor system, where the devices pertaining to the different processors are viewed as connecting to a standardized common bus. Regardless of the specific processor to which a device is directly connected, that device can be generally identified and accessed along the standardized common bus. PCIe is an example of a suitable standardized bus type that can be employed, where the devices for each processor node are represented as PCIe devices. Therefore, each of the devices would appear to the system software as a PCIe device. A PCIe controller can then be used to access the device by referring to the appropriate device identifier. This permits any device to be accessed on any of the processor nodes, without separate and individualized configurations or drivers for each separate processor node.

Abstract translation: 公开了一种用于配置用于多处理器系统的设备的方法，其中属于不同处理器的设备被视为连接到标准化公共总线。 无论设备直接连接到哪个特定处理器，该设备一般可以通过标准化的公共总线进行识别和访问。 PCIe是可以采用的合适的标准总线类型的示例，其中用于每个处理器节点的设备被表示为PCIe设备。 因此，每个设备将作为PCIe设备出现在系统软件中。 然后可以使用PCIe控制器通过参考适当的设备标识符来访问设备。 这允许在任何处理器节点上访问任何设备，而对于每个单独的处理器节点没有单独和个性化的配置或驱动程序。

公开(公告)号：US08549341B2

公开(公告)日：2013-10-01

申请号：US12201689

申请日：2008-08-29

Applicant: Ahmed Shahid ,  Kaushik Kuila ,  David T. Hass

Inventor： Ahmed Shahid ,  Kaushik Kuila ,  David T. Hass

IPC: G06F1/00

CPC classification number: G06F1/00 ,  G06F1/12 ,  G06F1/14 ,  H04J3/0667 ,  H04J3/0685

Abstract: A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.

Abstract translation: 提供了一种用于减少与多核，多线程处理器中的时间戳相关联的等待时间的系统和方法。 提供能够同时处理多个线程的处理器。 处理器包括多个核心，多个用于网络通信的网络接口，以及定时器电路，用于减少与用于使用精确时间协议的网络通信同步的时间戳相关联的等待时间。

公开(公告)号：US08499302B2

公开(公告)日：2013-07-30

申请号：US13226384

申请日：2011-09-06

Applicant: David T. Hass

Inventor： David T. Hass

IPC: G06F9/46 ,  G06F13/00 ,  G06F15/16 ,  G06F15/167 ,  H04L12/56

CPC classification number: H04L49/15 ,  G06F12/0813

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08438337B1

公开(公告)日：2013-05-07

申请号：US12571230

申请日：2009-09-30

Applicant: Gaurav Garg ,  David T. Hass

Inventor： Gaurav Garg ,  David T. Hass

IPC: G06F12/00

CPC classification number: G06F12/0815 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1024 ,  G06F2212/2542

Abstract: A system and method are provided for sharing data between a network including one or more network nodes. The network includes a number of individual network nodes and a home network node communicating with one another. The individual network nodes and the home network node include a plurality of processors and memory caches. The memory caches consist of private caches corresponding to individual processors, as well as shared caches which are shared among the plurality of processors of an individual node and accessible by the processors of the other network nodes. Each network node is capable of executing a hierarchy of data requests that originate in the private caches of an individual local network node. If no cache hits occur within the local network node, a conditional request is sent to the home network node to request data through the shared caches of the other network nodes.

Abstract translation: 提供了一种用于在包括一个或多个网络节点的网络之间共享数据的系统和方法。 网络包括多个单独的网络节点和彼此通信的家庭网络节点。 各个网络节点和家庭网络节点包括多个处理器和存储器高速缓存。 存储器高速缓存由对应于各个处理器的专用高速缓存组成，以及在单个节点的多个处理器之间共享且可由其他网络节点的处理器访问的共享高速缓存。 每个网络节点能够执行源自个别本地网络节点的专用高速缓存中的数据请求的层次。 如果在本地网络节点内没有发生高速缓存命中，则向家庭网络节点发送条件请求，以通过其他网络节点的共享缓存来请求数据。

公开(公告)号：US20120027029A1

公开(公告)日：2012-02-02

申请号：US13205420

申请日：2011-08-08

Applicant: Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

Inventor： Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

IPC: H04J99/00

CPC classification number: H04L49/901 ,  H04L49/9021 ,  H04L49/9042 ,  H04L69/02 ,  H04L69/22 ,  H04L69/26

Abstract: A method is provided for offloading packet protocol encapsulation from software. In operation, pointer information is received. Furthermore, packet protocol encapsulation is offloaded from software by assembling packets in hardware, using the pointer information.

Abstract translation: 提供了一种从软件中卸载数据包协议封装的方法。 在操作中，接收指针信息。 此外，使用指针信息，通过在硬件中组装分组，从软件卸载分组协议封装。

公开(公告)号：US08065456B2

公开(公告)日：2011-11-22

申请号：US12019576

申请日：2008-01-24

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F13/42 ,  G06F13/00 ,  G06F13/14 ,  G06F15/76

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores configured to support a plurality of software generated read or write instructions for interfacing with a star topology serial bus interface. The multiple-core processor has at least one of an internal fast messaging network or an interface switch interconnect configured to link the processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory. The fast messaging network or interface switch is also configured to be operably coupled to the star topology serial bus interface. In one aspect of an embodiment of the invention, the fast messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes.

Abstract translation: 高级处理器包括多个多线程处理器核，其被配置为支持多个软件产生的读取或写入指令，用于与星形拓扑串行总线接口进行接口。 多核处理器具有内部快速消息传递网络或配置成将处理器核心链接在一起的接口交换机互连中的至少一个，使得每个处理器核心具有到每个其他处理器核心的数据通路，而不经过存储器。 快速消息传递网络或接口交换机也被配置为可操作地耦合到星形拓扑串行总线接口。 在本发明的实施例的一个方面，快速消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。

公开(公告)号：US08015567B2

公开(公告)日：2011-09-06

申请号：US10931014

申请日：2004-08-31

Applicant: David T. Hass

Inventor： David T. Hass

IPC: G06F9/46 ,  G06F15/76 ,  G06F9/44 ,  G06F15/167 ,  G06F15/16 ,  H04L12/56

CPC classification number: H04L49/15 ,  G06F12/0813

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07941603B2

公开(公告)日：2011-05-10

申请号：US12627915

申请日：2009-11-30

Applicant: David T. Hass

Inventor： David T. Hass

IPC: G06F12/00 ,  G06F15/173

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/30

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07627717B2

公开(公告)日：2009-12-01

申请号：US11961884

申请日：2007-12-20

Applicant: David T. Hass ,  Abbas Rashid

Inventor： David T. Hass ,  Abbas Rashid

IPC: G06F12/00 ,  G06F15/16

CPC classification number: H04L45/52 ,  G06F12/0813 ,  G06F2212/154 ,  G06F2212/62 ,  H04L12/42 ,  H04L49/00 ,  H04L49/15 ,  H04L49/30 ,  H04L49/35

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。