公开(公告)号：US5999015A

公开(公告)日：1999-12-07

申请号：US902416

申请日：1997-07-29

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Bonnie I. Wang

IPC分类号： G06F7/48 ,  H03K19/177 ,  G06F7/38

CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/1774 ,  G06F7/48

摘要： A programmable logic device has subregions of programmable logic grouped together in logic regions. The subregions in each region share several control signals, which can be selected either from relatively global conductors on the device or from data inputs to the region. The control signals allow synchronous or asynchronous clearing of a register in each subregion. The control signals also allow synchronous loading of the register in each subregion, and the data loaded can be either one of the data inputs to the subregion (so-called lonely register operation) or a signal produced by the logic of the subregion.

摘要翻译： 可编程逻辑器件具有在逻辑区域中分组在一起的可编程逻辑的子区域。 每个区域中的子区域共享几个控制信号，其可以从设备上的相对全局导体或从数据输入到该区域来选择。 控制信号允许同步或异步清除每个子区域中的寄存器。 控制信号还允许每个子区域中寄存器的同步加载，并且加载的数据可以是该子区域的数据输入中的一个（所谓的孤独寄存器操作）或由该子区域的逻辑产生的信号。

公开(公告)号：US5850152A

公开(公告)日：1998-12-15

申请号：US834998

申请日：1997-04-07

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  David E. Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David W. Mendel ,  Craig S. Lytle ,  Robert R. N. Bielby ,  Kerry Veenstra

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  David E. Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David W. Mendel ,  Craig S. Lytle ,  Robert R. N. Bielby ,  Kerry Veenstra

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

公开(公告)号：US5850151A

公开(公告)日：1998-12-15

申请号：US834996

申请日：1997-04-07

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  David E. Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David W. Mendel ,  Craig S. Lytle ,  Robert R. N. Bielby ,  Kerry Veenstra

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  David E. Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David W. Mendel ,  Craig S. Lytle ,  Robert R. N. Bielby ,  Kerry Veenstra

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

摘要翻译： 可编程逻辑阵列集成电路器件包括以有意义的行和列的二维阵列布置在器件上的多个可编程逻辑区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。

公开(公告)号：US5659717A

公开(公告)日：1997-08-19

申请号：US508401

申请日：1995-07-31

申请人： John Tse ,  David W. Mendel

发明人： John Tse ,  David W. Mendel

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Improved circuit partitioning methods are provided which combine the advantage of multiple starting positions of the random initial placement approach with the advantage of optimal starting positions of the greedy initial placement approach, by starting with greedy initial placement and modifying partitioning constraints on subsequent passes so that each pass begins in a new position, In addition, the partitioning goals of interconnection minimization and resource utilization efficiency may be prioritized according to a design goal by manipulating the manner in which partitioning constraints are changed during each partitioning pass. Furthermore a user may adjust the weight of the benefits for eliminating existing interconnections and the weight of the penalties for adding new interconnections in accordance with a design goal.

摘要翻译： 提供了改进的电路划分方法，其结合了随机初始放置方法的多个起始位置的优点和贪婪初始放置方法的最佳起始位置的优点，从贪婪初始放置开始，并修改后续通过的分区约束， 通过从一个新的位置开始。另外，可以根据设计目标优化互连最小化和资源利用效率的分区目标，通过操纵在每次分区过程中分区约束被改变的方式。 此外，用户可以调整用于消除现有互连的益处的重量以及根据设计目标添加新互连的惩罚的重量。

公开(公告)号：US09111042B1

公开(公告)日：2015-08-18

申请号：US13428781

申请日：2012-03-23

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： G06F13/38

CPC分类号： G06F13/385

摘要： Systems and methods are disclosed for precisely determining the delay between data being received at the pins of a circuit and being processed by gearbox circuitry, to being processed by a time-stamp unit of the circuit. In an exemplary embodiment, the gearbox circuitry may output a data valid signal which may be monitored by the time-stamp unit. By monitoring the data valid signal, the time-stamp unit may synchronize a local state machine with the internal state of the gearbox circuitry and thus determine the total delay through the combined processing circuitry with high accuracy.

摘要翻译： 公开了系统和方法，用于精确地确定在电路的引脚处接收并由齿轮箱电路处理的数据之间的延迟，以被电路的时间戳单元处理。 在示例性实施例中，齿轮箱电路可以输出可由时间戳单元监视的数据有效信号。 通过监视数据有效信号，时间戳单元可以使局部状态机与变速箱电路的内部状态同步，从而以高精度确定通过组合处理电路的总延迟。

公开(公告)号：US08886856B1

公开(公告)日：2014-11-11

申请号：US13165762

申请日：2011-06-21

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/00 ,  G06F13/12 ,  G06F13/38

CPC分类号： G06F13/4265

摘要： One embodiment relates to an integrated circuit configured to communicate a low-latency word category over a multi-lane link. A transmitter controller is configured to transmit words belonging to the low-latency word category only over a designated lane of the multi-lane link and to transmit words belonging to non-low-latency word categories over any available lane of the multi-lane link. A receiver controller may be configured to determine a word category of a word received over the designated lane and, if the word category is determined to be the low-latency word category, then read the word from the designated lane before lane-to-lane deskew is completed. Other embodiments, aspects, and features of the invention are also disclosed.

摘要翻译： 一个实施例涉及被配置为在多通道链路上传送低延迟字类别的集成电路。 发射机控制器被配置为仅在多通道链路的指定车道上传送属于低延迟字类别的字，并且在多车道链路的任何可用车道上传送属于非低延迟字类别的字 。 接收机控制器可以被配置为确定通过指定的车道接收的字的单词类别，并且如果将字类别确定为低延迟字类别，则在车道到车道之前从指定车道读取该字 偏斜校正完成。 还公开了本发明的其它实施例，方面和特征。

公开(公告)号：US08810299B2

公开(公告)日：2014-08-19

申请号：US13648146

申请日：2012-10-09

申请人： Gregg William Baeckler ,  David W. Mendel

发明人： Gregg William Baeckler ,  David W. Mendel

IPC分类号： G06F1/04 ,  H03K3/00

CPC分类号： G06F1/08 ,  G06F1/12

摘要： Control circuitry and adjustable clock signal generation circuitry is provided to control the signal transmission rate for electronic devices and systems of electronic devices. The control circuitry may receive status signals indicating current clock rates of a signal transmitting and receiving circuit as well as current processing capacity from the signal receiving circuit. The control circuitry may then generate control signals which control adjustable clock signal generation circuitry. The adjustable clock signal generation circuitry may be used to adjust the rate of generated clock signals for the signal transmitting and receiving circuits which can increase or decrease the signal transmission rate between those circuits.

摘要翻译： 提供控制电路和可调时钟信号产生电路以控制电子设备和电子设备系统的信号传输速率。 控制电路可以从信号接收电路接收指示信号发送和接收电路的当前时钟速率以及当前处理能力的状态信号。 控制电路然后可以产生控制可调时钟信号产生电路的控制信号。 可调时钟信号产生电路可以用于调整信号发射和接收电路产生的时钟信号的速率，这些信号可以增加或减少这些电路之间的信号传输速率。

公开(公告)号：US08751998B2

公开(公告)日：2014-06-10

申请号：US13369218

申请日：2012-02-08

申请人： David W. Mendel ,  Marwan A. Khalaf ,  Renxin Xia

发明人： David W. Mendel ,  Marwan A. Khalaf ,  Renxin Xia

IPC分类号： G06F11/22 ,  G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5022

摘要： Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a simulation program to simulate partial reconfiguration of the logic design. The wrapper module of the simulatable source file receives a run-time parameter. In various embodiments, the logic description is a synthesizable source file. The synthesizable source file is a source file that is used by a synthesis tool to compile the source file into hardware. The wrapper module of the synthesizable source receives a compile-time parameter.

摘要翻译： 公开了一种模拟可编程逻辑器件（PLD）的部分重新配置的方法。 封装模块被并入到可以在PLD中实现的逻辑描述中。 封装模块代表第一逻辑设计。 响应于接收参数，包装器模块改变以表示第二逻辑设计。 根据各种实施例，逻辑描述是可模拟的源文件。 可模拟的源文件是由仿真程序用于模拟逻辑设计的部分重新配置的源文件。 可模拟源文件的包装器模块接收运行时参数。 在各种实施例中，逻辑描述是可合成的源文件。 可合成的源文件是由合成工具用来将源文件编译成硬件的源文件。 可合成源的包装器模块接收编译时参数。

公开(公告)号：US08686753B1

公开(公告)日：2014-04-01

申请号：US13441566

申请日：2012-04-06

申请人： Alan Louis Herrmann ,  David W. Mendel

发明人： Alan Louis Herrmann ,  David W. Mendel

IPC分类号： H03K19/177 ,  G01R31/28

CPC分类号： H03K19/017581 ,  G01R31/31705 ,  G01R31/318519 ,  H03K19/17756

摘要： Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.

摘要翻译： 嵌入式逻辑在部分可重新配置的可编程逻辑器件（PLD）中实现，从而允许在部分重新配置之后调试实现的逻辑实例。 PLD收到了几个逻辑实例。 逻辑的一个实例化在PLD内的可重新配置的逻辑区域中实现。 逻辑的实例包括在逻辑的可重新配置区域和PLD内的固定的逻辑区域之间提供恒定接口的端口。 端口可以​​从在可重新配置的逻辑区域内实现的探测点接收信号。 端口可以​​将信号提供给在固定的逻辑区域内实现的信号接口。 此外，嵌入式逻辑分析器可以被实现在逻辑的可重新配置区域或逻辑的固定区域中。 嵌入式逻辑分析仪从探测点接收信号，并向外部计算系统提供信号可见性。

公开(公告)号：US20130007687A1

公开(公告)日：2013-01-03

申请号：US13369218

申请日：2012-02-08

申请人： David W. Mendel ,  Marwan A. Khalaf ,  Renxin Xia

发明人： David W. Mendel ,  Marwan A. Khalaf ,  Renxin Xia

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5022

摘要： Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a simulation program to simulate partial reconfiguration of the logic design. The wrapper module of the simulatable source file receives a run-time parameter. In various embodiments, the logic description is a synthesizable source file. The synthesizable source file is a source file that is used by a synthesis tool to compile the source file into hardware. The wrapper module of the synthesizable source receives a compile-time parameter.

摘要翻译： 公开了一种模拟可编程逻辑器件（PLD）的部分重新配置的方法。 封装模块被并入到可以在PLD中实现的逻辑描述中。 封装模块代表第一逻辑设计。 响应于接收参数，包装器模块改变以表示第二逻辑设计。 根据各种实施例，逻辑描述是可模拟的源文件。 可模拟的源文件是由仿真程序用于模拟逻辑设计的部分重新配置的源文件。 可模拟源文件的包装器模块接收运行时参数。 在各种实施例中，逻辑描述是可合成的源文件。 可合成的源文件是由合成工具用来将源文件编译成硬件的源文件。 可合成源的包装器模块接收编译时参数。