Partial reconfiguration and in-system debugging
    1.
    发明授权
    Partial reconfiguration and in-system debugging 有权
    部分重新配置和在系统调试

    公开(公告)号:US08686753B1

    公开(公告)日:2014-04-01

    申请号:US13441566

    申请日:2012-04-06

    IPC分类号: H03K19/177 G01R31/28

    摘要: Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.

    摘要翻译: 嵌入式逻辑在部分可重新配置的可编程逻辑器件(PLD)中实现,从而允许在部分重新配置之后调试实现的逻辑实例。 PLD收到了几个逻辑实例。 逻辑的一个实例化在PLD内的可重新配置的逻辑区域中实现。 逻辑的实例包括在逻辑的可重新配置区域和PLD内的固定的逻辑区域之间提供恒定接口的端口。 端口可以​​从在可重新配置的逻辑区域内实现的探测点接收信号。 端口可以​​将信号提供给在固定的逻辑区域内实现的信号接口。 此外,嵌入式逻辑分析器可以被实现在逻辑的可重新配置区域或逻辑的固定区域中。 嵌入式逻辑分析仪从探测点接收信号,并向外部计算系统提供信号可见性。

    Distributed burst error protection
    2.
    发明授权
    Distributed burst error protection 有权
    分布式突发错误保护

    公开(公告)号:US08943393B1

    公开(公告)日:2015-01-27

    申请号:US13310628

    申请日:2011-12-02

    IPC分类号: G06F11/10

    摘要: A method of protecting digital words traversing multiple data paths is presented. The method identifies a number of bits for a header of a digital word and determines a number of protection bits for the header. A bit value for each of the protection bits is computed, and the computed bit values of the protection bits are transmitted through one or more data paths.

    摘要翻译: 提出了一种保护数字字遍历多个数据路径的方法。 该方法识别数字字的头部的位数,并且确定头部的保护位数。 计算每个保护位的位值,并且通过一个或多个数据路径发送保护位的计算位值。

    Reconfigurable logic block
    3.
    发明授权

    公开(公告)号:US08572538B2

    公开(公告)日:2013-10-29

    申请号:US13369226

    申请日:2012-02-08

    IPC分类号: G06F17/50 H03K19/173

    摘要: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

    Multi-lane communication with measurable latency
    4.
    发明授权
    Multi-lane communication with measurable latency 有权
    具有可测量延迟的多通道通信

    公开(公告)号:US08355477B1

    公开(公告)日:2013-01-15

    申请号:US12762995

    申请日:2010-04-19

    申请人: David W. Mendel

    发明人: David W. Mendel

    IPC分类号: H04L7/00

    CPC分类号: H04L25/14

    摘要: Methods and structures are provided for multi-lane data communication with measurable latency. In a particular embodiment, part of a parallel data set is transmitted from a first device to a second device on a plurality of slave lanes and another part of the data set is transmitted from the first device to the second device on a master lane. A known master delay is applied to data in the master lane that is greater than or equal to the known maximum skew between the lanes. The slave lanes are delayed as needed to align their data with the master lane. In one embodiment, part of the known master lane delay is applied on the first device and another part is applied on the second device. In another embodiment, all of the known master lane delay is applied on the first device and none of it is applied on the second device. In another embodiment, all of the known master lane delay is applied on the second device and none of it is applied on the first device. In another embodiment, part or all of the master lane delay is applied on the link between devices.

    摘要翻译: 为多通道数据通信提供了可测量延迟的方法和结构。 在特定实施例中,并行数据集的一部分在多个从属车道上从第一装置发送到第二装置,并且数据组的另一部分在主车道上从第一装置发送到第二装置。 已知的主延迟被应用于主通道中大于或等于车道之间的已知最大偏差的数据。 从车道根据需要延时,以将其数据与主车道对准。 在一个实施例中,已知主通道延迟的一部分被施加在第一设备上,而另一部分被施加在第二设备上。 在另一个实施例中,所有已知的主通道延迟被施加在第一设备上,并且它们都不被施加在第二设备上。 在另一个实施例中,所有已知的主车道延迟被施加在第二设备上,并且它们都不被施加在第一设备上。 在另一个实施例中,主通道延迟的部分或全部被应用在设备之间的链路上。

    Transceiver system with reduced latency uncertainty
    5.
    发明申请
    Transceiver system with reduced latency uncertainty 有权
    收发器系统具有降低的延迟不确定性

    公开(公告)号:US20090161738A1

    公开(公告)日:2009-06-25

    申请号:US12283652

    申请日:2008-09-15

    IPC分类号: H04L7/00 H04B1/38

    CPC分类号: H04L25/14

    摘要: A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

    摘要翻译: 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中,收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中,收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中,收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中,通过在发射机锁相环(PLL)中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中,这通过可选地使发射机分频器(其产生发射机并行时钟)作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中,通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性,使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中,由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零,因为位拖动器滑动位,以补偿由字对准器执行的位移。

    Wide exclusive or and wide-input and for PLDS
    7.
    发明授权
    Wide exclusive or and wide-input and for PLDS 失效
    广泛的独占或广泛的输入和PLDS

    公开(公告)号:US06043676A

    公开(公告)日:2000-03-28

    申请号:US825821

    申请日:1997-03-28

    IPC分类号: H03K19/177

    CPC分类号: H03K19/177

    摘要: A programmable logic device (10) has a number of programmable logic elements (LES) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). An LAB incorporates one or more wide-input AND gates (74) for selectively combining the outputs of any number of LEs and producing a signal that is a logical combination of any number of its LEs. In variations of the invention, input signals may be selectively coupled to an AND gate by means of an OR gate (78) and may be selectively inverted by means of an XOR gate (76). A digital information processing system (500) incorporating the invention is disclosed. Various circuit techniques are provided for efficient implementation of a fast and wide exclusive OR or exclusive NOR function. A logic array block is equipped with a dedicated exclusive OR circuit with programmable inputs connected to selected terms from various logic cells, or outputs of the various logic cells. Another embodiment allows creating an embedded chain of exclusive OR gates to implement a wide exclusive OR gate by cascading a smaller exclusive OR gate within several logic cells.

    摘要翻译: 可编程逻辑器件(10)具有多个可编程逻辑元件(LES)(12),它们被分组在多个逻辑阵列块(LAB)中。 LAB包括一个或多个宽输入与门(74),用于选择性地组合任何数量的LE的输出,并产生作为任何数量的LE的逻辑组合的信号。 在本发明的变型中,输入信号可以通过或门(78)选择性地耦合到与门,并且可以通过异或门(76)选择性地反相。 公开了结合本发明的数字信息处理系统(500)。 提供了各种电路技术,用于有效地实现快速和宽泛的异或或异或NOR功能。 逻辑阵列块配备有专用异或电路,其可编程输入连接到来自各种逻辑单元的选定项或各种逻辑单元的输出。 另一实施例允许创建异或门的嵌入链以通过级联多个逻辑单元内的较小的异或门来实现宽的异或门。

    Integrated circuits with clock selection circuitry
    9.
    发明授权
    Integrated circuits with clock selection circuitry 有权
    具有时钟选择电路的集成电路

    公开(公告)号:US09515880B1

    公开(公告)日:2016-12-06

    申请号:US13338898

    申请日:2011-12-28

    摘要: An integrated circuit device may include processing circuits that can be dynamically reconfigured to perform different tasks each of which utilizes different system clock resources. The device may include clock selection circuitry that can selectively route desired clock signals to corresponding processing circuits. The clock signal provided to each processing circuit may be selected based on a current configuration of that processing circuit. Client processing circuits in a network switch may be coupled to interchangeable client networks. The client processing circuits may be dynamically reconfigured based on characteristics of the client networks that are currently coupled to the network switch. By dynamically selecting which clock resources are provided to the processing circuits, clock resources such as global clock signals that are relatively scarce may be reserved for processing circuits that can only function with the relatively scarce clock resources. Arranged in this way, clock resource utilization may be continuously optimized.

    摘要翻译: 集成电路设备可以包括可以动态地重新配置以执行不同的任务的处理电路,每个任务利用不同的系统时钟资源。 该装置可以包括时钟选择电路,其可以选择性地将期望的时钟信号路由到相应的处理电路。 可以基于该处理电路的当前配置来选择提供给每个处理电路的时钟信号。 网络交换机中的客户端处理电路可以耦合到可互换的客户端网络。 可以基于当前耦合到网络交换机的客户端网络的特性来动态地重新配置客户端处理电路。 通过动态地选择哪些时钟资源被提供给处理电路,诸如相对稀少的全局时钟信号的时钟资源可以被保留用于只能用相对稀少的时钟资源起作用的处理电路。 以这种方式安排,可以不断优化时钟资源利用。

    Apparatus and methods for time-multiplex field-programmable gate arrays
    10.
    发明授权
    Apparatus and methods for time-multiplex field-programmable gate arrays 有权
    时域复用现场可编程门阵列的装置和方法

    公开(公告)号:US08543955B1

    公开(公告)日:2013-09-24

    申请号:US12716999

    申请日:2010-03-03

    IPC分类号: G06F17/50

    摘要: A time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry, programmable interconnect circuitry, and a plurality of context registers. A user's circuit can be mapped to the programmable logic circuitry, the programmable interconnect circuitry, and the plurality of context registers without the user's intervention in mapping the design.

    摘要翻译: 时间复用的现场可编程门阵列(TM-FPGA)包括可编程逻辑电路,可编程互连电路和多个上下文寄存器。 用户的电路可以映射到可编程逻辑电路,可编程互连电路和多个上下文寄存器,而无需用户对设计进行映射。