公开(公告)号：US08648653B2

公开(公告)日：2014-02-11

申请号：US12650546

申请日：2009-12-31

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03K5/00

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract translation: 提供一种减少电路干扰的方法和装置。 提供管理策略，以减少参考杂散和电路干扰。 管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。 这些技术可以单独使用，或者优选地彼此组合使用。

公开(公告)号：US08421529B2

公开(公告)日：2013-04-16

申请号：US12650543

申请日：2009-12-31

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03K5/00

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

公开(公告)号：US07477879B1

公开(公告)日：2009-01-13

申请号：US11172039

申请日：2005-06-30

Applicant: Ramkishore Ganti ,  Caiyi Wang

Inventor： Ramkishore Ganti ,  Caiyi Wang

IPC: H04B1/40

CPC classification number: H04B1/0475 ,  H04B1/28

Abstract: A transceiver system including a common receiver and transmitter oscillator. The transceiver system may include transmitter circuitry, receiver circuitry, and a first oscillator. The first oscillator may provide a transmit frequency to a mixer in the transmitter circuitry to generate a transmitter RF signal. Furthermore, the first oscillator may also provide the transmit frequency to a first stage mixer in the receiver circuitry to down-convert a receiver RF signal from a receive frequency to an intermediate frequency (IF). The receiver circuitry may include a second oscillator and a second stage mixer. The second oscillator may provide an IF frequency to the second stage mixer to down-convert receiver signals at IF to a lower frequency. The receiver circuitry may filter out transmitter RF feedthrough signals without using a SAW filter. The transmitter circuitry, the receiver circuitry, and the first oscillator may be included in a single IC.

Abstract translation: 一种收发机系统，包括公共接收机和发射机振荡器。 收发机系统可以包括发射机电路，接收机电路和第一振荡器。 第一振荡器可以向发射机电路中的混频器提供发射频率以产生发射机RF信号。 此外，第一振荡器还可以向接收机电路中的第一级混频器提供发射频率，以将接收机RF信号从接收频率下变频到中频（IF）。 接收器电路可以包括第二振荡器和第二级混频器。 第二振荡器可以向第二级混频器提供IF频率以在IF处将接收机信号下变频到较低的频率。 接收器电路可以滤除发射器RF馈通信号而不使用SAW滤波器。 发射机电路，接收机电路和第一振荡器可以被包括在单个IC中。

公开(公告)号：US07376396B2

公开(公告)日：2008-05-20

申请号：US11096133

申请日：2005-03-31

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H04B1/40 ,  H03C1/52

CPC classification number: H04B1/403

Abstract: A ratiometric transmit path architecture for communication systems and related methods are disclosed. This ratiometric transmit path architecture utilizes a single local oscillator signal and dividers to provide mixing signals for intermediate frequency (IF) mixing circuitry and feedback mixing circuitry, thereby eliminating the need for separate IF and radio frequency (RF) voltage controlled oscillators (VCOs) in prior solutions.

Abstract translation: 公开了用于通信系统和相关方法的比例传输路径架构。 这种比例传输路径架构利用单个本地振荡器信号和分频器来为中频（IF）混频电路和反馈混频电路提供混频信号，从而消除对单独的IF和射频（RF）压控振荡器（VCO）的需要 以前的解决方案。

公开(公告)号：US07353011B2

公开(公告)日：2008-04-01

申请号：US11180267

申请日：2005-07-13

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H04B7/00 ,  H04B1/06

CPC classification number: H03L7/193 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199 ,  H03L7/23 ,  H03L2207/06

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

Abstract translation: 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。 第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。

公开(公告)号：US07292091B1

公开(公告)日：2007-11-06

申请号：US11170380

申请日：2005-06-29

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03K5/00

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

公开(公告)号：US06311050B1

公开(公告)日：2001-10-30

申请号：US09087174

申请日：1998-05-29

Applicant: David R. Welland ,  Caiyi Wang ,  Donald A. Kerth

Inventor： David R. Welland ,  Caiyi Wang ,  Donald A. Kerth

IPC: H04Q720

CPC classification number: H03L7/10 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/199 ,  H03L7/23

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. The invention disclosed avoids the need for a traditional varactor implementation in the VCO, for a traditional large capacitor component in the loop filter, and for component trimming during processing and thereby provides a high-frequency frequency synthesizer that may be fully integrated on a single chip except for an external inductor.

Abstract translation: 公开了一种用于合成高频信号的方法和装置，其克服了与现有实施相关的集成问题，同时满足苛刻的相位噪声和其他杂质要求。 在一个实施例中，公开了具有可变电容的压控振荡器（VCO）的锁相环（PLL）频率合成器，该可变电容包括连续可变电容的离散可变电容。 离散可变电容可以提供可变电容的粗调谐调节，并且连续可变电容可以提供可变电容的精细调谐。 所公开的发明避免了在VCO中对传统的变容二极管实现的需要，对于环路滤波器中的传统大电容器组件以及在处理期间的组件调整，从而提供可以完全集成在单个芯片上的高频频率合成器 外部电感除外。

公开(公告)号：US6150891A

公开(公告)日：2000-11-21

申请号：US87488

申请日：1998-05-29

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H03D7/16 ,  H03L7/087 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03L7/23 ,  H04B1/26 ,  H04B1/30 ,  H03B5/08 ,  H03L7/06 ,  H03L7/091 ,  H03L7/16

CPC classification number: H03L7/099 ,  H03D7/163 ,  H03L7/087 ,  H03L7/187 ,  H03L7/199 ,  H03L7/23 ,  H04B1/26 ,  H03J2200/10 ,  H04B1/30

Abstract: The synthesis of high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock by using a shift register. The shift register may be clocked by another clock signal at a higher frequency than the divided version of the VCO output clock. The phase differences between the plurality of phase shifted signals and a divided version of a reference clock may then be detected and converted to the analog control signals.

Abstract translation: 诸如无线通信信号的高频信号的合成包括具有可变电容压控振荡器（VCO）的锁相环（PLL）频率合成器，该可变电容压控振荡器（VCO）具有连续可变电容的离散可变电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过使用移位寄存器首先从VCO输出时钟的分割版本生成多个相移信号来导出模拟控制信号。 移位寄存器可以以比VCO输出时钟的分频版本更高的频率由另一个时钟信号来计时。 然后可以检测多个相移信号和参考时钟的分割版本之间的相位差并转换成模拟控制信号。

公开(公告)号：US08669816B2

公开(公告)日：2014-03-11

申请号：US13273231

申请日：2011-10-14

Applicant: Yen-Horng Chen ,  Augusto Marques ,  Caiyi Wang

Inventor： Yen-Horng Chen ,  Augusto Marques ,  Caiyi Wang

IPC: H03L7/00

CPC classification number: H03L7/099 ,  H03L1/00 ,  H03L1/02 ,  H03L2207/06 ,  H03L2207/50

Abstract: An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency control signal. The at least one controllable oscillator further includes at least one compensation module including an output arranged to provide at least one compensation signal. The at least one compensation module includes an integrator component arranged to receive at an input thereof a signal that is representative of a difference between the indication of the frequency control signal and a reference signal, and to output an integrated difference signal. The at least one compensation module is arranged to generate the at least one compensation signal based at least partly on the integrated difference signal output by the integrator component.

Abstract translation: 集成电路装置包括至少一个包括第一控制端口和至少一个另外的控制端口的可控振荡器，至少一个频率控制模块，其包括布置成提供频率控制信号的输出。 所述至少一个可控振荡器还包括至少一个补偿模块，该补偿模块包括布置成提供至少一个补偿信号的输出。 所述至少一个补偿模块包括积分器部件，其被布置为在其输入处接收表示所述频率控制信号的指示与参考信号之间的差异的信号，并输出积分差分信号。 至少一个补偿模块被布置成至少部分地基于由积分器组件输出的积分差分信号来产生至少一个补偿信号。

公开(公告)号：US08531322B2

公开(公告)日：2013-09-10

申请号：US13450263

申请日：2012-04-18

Applicant: Changhua Cao ,  Xiaochuan Guo ,  Yen-Horng Chen ,  Caiyi Wang

Inventor： Changhua Cao ,  Xiaochuan Guo ,  Yen-Horng Chen ,  Caiyi Wang

IPC: H03M1/48

CPC classification number: G04F10/005

Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.

Abstract translation: 提供了一种时间 - 数字转换器的实施例，包括延迟级矩阵和测量电路。 延迟级矩阵包括与其耦合的第一和第二延迟线，并且被布置成在第一和第二延迟线中从起始延迟级传播转换信号，其中第一和第二延迟线中的每一个包括相同的数字 的延迟级串联耦合，第一和第二延迟线之一中的每个延迟级耦合到另一个延迟线中的对应的延迟级并且可操作以产生延迟信号。 测量电路被设置为通过使用测量信号对延迟信号进行采样来确定沿延迟级传播的转换信号的时间，以生成并保持时间的数字表示。