公开(公告)号：US08249188B2

公开(公告)日：2012-08-21

申请号：US13175589

申请日：2011-07-01

Applicant: Deqiang Song ,  Dawei Huang ,  Drew G. Doblar ,  Michael Stephen Harwood ,  Nirmal C. Warke

Inventor： Deqiang Song ,  Dawei Huang ,  Drew G. Doblar ,  Michael Stephen Harwood ,  Nirmal C. Warke

IPC: H04L27/00

CPC classification number: H04L25/068

Abstract: A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.

Abstract translation: 提供了一种用于为接收机接收的一组输入信号构造过采样波形的机制。 在一个实现中，过采样波形通过接收器和波形构造机构（WCM）之间的协作来构造。 接收机接收输入信号，一次对入局信号的子集进行采样，将样本值的子集存储到一组寄存器中，随后将样本值的子集提供给WCM。 WCM依次对样本值的子集进行排序，将它们组织成正确的顺序，并将它们“缝合”在一起，以构成输入信号集合的过采样波形。 通过接收机和WCM之间的适当协作，并且在WCM上具有适当的处理逻辑，可以为输入信号构造过采样波形，而不需要接收机上的大量资源。

公开(公告)号：US20110103458A1

公开(公告)日：2011-05-05

申请号：US12612449

申请日：2009-11-04

Applicant: Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

Inventor： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

IPC: H04L27/01 ,  H04L27/00 ,  H03K5/153

CPC classification number: H04L25/03878 ,  H04L25/03146

Abstract: An asymmetric DFE receiver circuit. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.

Abstract translation: 不对称DFE接收器电路。 接收器电路包括：电压测量单元，被配置为确定接收信号的信号电压;以及比较器单元，被配置为计算信号电压和评估阈值电压之间的差，并将该差与中点电压的值进行比较。 比较器单元被配置为如果差值大于中点电压值则产生第一控制信号，或者如果信号电压小于中点电压值则产生第二控制信号。 所述接收机包括：调整电路，被配置为如果产生所述第一控制信号并且如果产生所述第二控制信号则将所述评估阈值电压调整到所述信号电压。 调整速率可以根据接收到的信号是转换位还是非转换位而变化。

公开(公告)号：US20100238993A1

公开(公告)日：2010-09-23

申请号：US12409236

申请日：2009-03-23

Applicant: Dawei Huang ,  Muthukumar Vairavan ,  Dong Joon Yoon ,  Drew G. Doblar

Inventor： Dawei Huang ,  Muthukumar Vairavan ,  Dong Joon Yoon ,  Drew G. Doblar

IPC: H04L27/01

CPC classification number: H04L25/03057 ,  H04L7/0337 ,  H04L2025/03503

Abstract: A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel.

Abstract translation: 公开了一种数据通信系统和方法。 该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。 接收机使用判决反馈均衡器（DFE）和FIR来均衡接收到的数据信号。 接收机采样数据信号以确定误差信号，并使用误差信号来适应FIR的前置光标抽头系数，FIR的一个或多个后置标签抽头系数，恢复时钟的相位的设置，以及 DFE的系数。 为了适应设置，接收机根据在单个时钟周期内从数据信号中获取的错误样本来确定误差信号。 为了确定误差信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。

公开(公告)号：US20100177841A1

公开(公告)日：2010-07-15

申请号：US12353717

申请日：2009-01-14

Applicant: Dong J. Yoon ,  Dawei Huang ,  Drew G. Doblar

Inventor： Dong J. Yoon ,  Dawei Huang ,  Drew G. Doblar

IPC: H04L27/00

CPC classification number: H03M9/00 ,  H03K3/00 ,  H03L7/0814

Abstract: A system and method include a SerDes transmitter comprising a digital block operating in a digital voltage domain. The digital block can be configured to receive a first group of bits of data in parallel and store history bits from another group of data. The SerDes transmitter can further comprise an analog block operating in an analog voltage domain. The analog block can be configured to receive the first group of bits of data from the digital block, receive the history bits from the digital block, generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits, align each combination of bits to a phase of a multi-phase clock; and input each combination into an output driver.

Abstract translation: 一种系统和方法包括一个SerDes发射机，其包括以数字电压域工作的数字模块。 数字块可以被配置为并行地接收数据的第一组数据并存储来自另一组数据的历史比特。 SerDes发射机还可以包括在模拟电压域中工作的模拟块。 模拟块可以被配置为从数字块接收第一组数据，从数字块接收历史比特，从第一比特组生成具有一个或多个比特的比特的多个组合， 来自历史比特的更多比特，将每个比特组合对齐到多相时钟的相位; 并将每个组合输入到输出驱动器中。

公开(公告)号：US20090252212A1

公开(公告)日：2009-10-08

申请号：US12061217

申请日：2008-04-02

Applicant: Gabriel Risk ,  Dawei Huang ,  Drew Doblar

Inventor： Gabriel Risk ,  Dawei Huang ,  Drew Doblar

IPC: H04L27/01

CPC classification number: H04L25/0288 ,  H04L25/03343

Abstract: A method and apparatus for equalizing a reflection in a reflective high speed serial link. The method involves obtaining an amplitude and delay time of a compensating pulse that is transmitted in response to a pulse transmitted on the serial link. The apparatus comprises a programmable delay element and a driver stage configured to transmit a delayed and amplitude adjusted version of a pulse transmitted on the serial link. A method for equalizing a plurality of reflections in a reflective high speed serial link. The method involves obtaining an amplitude and delay time of a first compensating pulse and an amplitude and delay time of a second compensating pulse. The method further involves transmitting the first compensating and second compensating pulses in response to a pulse transmitted on the serial link.

Abstract translation: 一种用于均衡反射高速串行链路中的反射的方法和装置。 该方法包括获得响应于在串行链路上发送的脉冲而发送的补偿脉冲的幅度和延迟时间。 该装置包括可编程延迟元件和驱动器级，其被配置为传送在串行链路上传输的脉冲的延迟和幅度调整版本。 一种用于均衡反射高速串行链路中的多个反射的方法。 该方法包括获得第一补偿脉冲的幅度和延迟时间以及第二补偿脉冲的幅度和延迟时间。 该方法还包括响应于在串行链路上发送的脉冲发送第一补偿和第二补偿脉冲。

公开(公告)号：US08599909B2

公开(公告)日：2013-12-03

申请号：US12850535

申请日：2010-08-04

Applicant: Drew G. Doblar ,  Dawei Huang ,  Deqiang Song

Inventor： Drew G. Doblar ,  Dawei Huang ,  Deqiang Song

IPC: H04B3/46

CPC classification number: H04L25/03057 ,  H04L25/061 ,  H04L25/14

Abstract: This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.

Abstract translation: 本公开描述了使用SerDes接收机在任务模式下确定串行器/解串器（SerDes）接收器的电压余量（或余量）的系统和方法。 这通过在相同的硬件（或软件或硬件和软件的组合）上进行裕度确定和抽头权重适配的时分复用来完成。 换句话说，SerDes接收机的一些部分（例如，错误限制器和适配模块）可以在不同的时间用于两个不同的任务，而不降低接收机的有效性或带宽。 因此，所公开的系统和方法允许SerDes接收机在任务模式下确定SerDes余量，并且在接收器芯片上没有任何额外的硬件或电路。

公开(公告)号：US20130230272A1

公开(公告)日：2013-09-05

申请号：US13410113

申请日：2012-03-01

Applicant: Kannan Raj ,  Dawei Huang ,  Nicholas E. Aneshansley ,  Theresa Sze ,  David K. McElfresh

Inventor： Kannan Raj ,  Dawei Huang ,  Nicholas E. Aneshansley ,  Theresa Sze ,  David K. McElfresh

IPC: G02B6/12

CPC classification number: G02B6/428 ,  G02B6/4246 ,  G02B6/4269 ,  G02B6/4274

Abstract: A chip assembly configuration includes an substrate with an integrated circuit on one side and a conversion mechanism on the other side. The integrated circuit and the conversion mechanism are electrically coupled by a short electrical transmission line through the substrate. Moreover, the conversion mechanism converts signals between an electrical and an optical domain, thereby allowing high-speed communication between the integrated circuit and other components and devices using optical communication (for example, in an optical fiber or an optical waveguide).

Abstract translation: 芯片组装配置包括在一侧具有集成电路的基板和另一侧上的转换机构。 集成电路和转换机构通过穿过衬底的短电传输线电耦合。 此外，转换机构在电区域和光学域之间转换信号，从而允许集成电路与使用光通信的其他部件和设备（例如，在光纤或光波导中）之间的高速通信。

公开(公告)号：US08446985B2

公开(公告)日：2013-05-21

申请号：US12343426

申请日：2008-12-23

Applicant: Drew G. Doblar ,  Dawei Huang ,  Deqiang Song

Inventor： Drew G. Doblar ,  Dawei Huang ,  Deqiang Song

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC classification number: H04L7/0008 ,  G06F1/10 ,  H04L25/061

Abstract: A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.

Abstract translation: 提供一种用于降低高频时钟信号的占空比失真的放大的方法和装置。 数据信号通过第一通道发送到接收器。 时钟信号通过第二通道发送到接收器。 在时钟信号被接收机使用以从数据信号恢复数据之前，时钟信号被滤波以基本上从其中去除低频分量。

公开(公告)号：US20130077723A1

公开(公告)日：2013-03-28

申请号：US13245533

申请日：2011-09-26

Applicant: Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Osman Javed ,  Hongtao Zhang

Inventor： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Osman Javed ,  Hongtao Zhang

IPC: H04L7/02

CPC classification number: H04L7/0054 ,  H04L7/0062

Abstract: In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(−1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.

Abstract translation: 在接收机电路中，节点接收从发射机电路传送数据的信号。 此外，接收机电路中的时钟数据恢复（CDR）电路从接收到的信号中恢复一个速率时钟信号。 CDR电路恢复时钟信号，而不会将信号的第一脉冲响应前兆相对于信号的脉冲响应光标收敛到大约零（例如，随着第一脉冲响应前兆h（-1）收敛到非零， - 零值）。 此外，第一脉冲响应前体对应于除了当前样本以外的脉冲响应的至少一个前体或后脉冲。

公开(公告)号：US08243866B2

公开(公告)日：2012-08-14

申请号：US12116329

申请日：2008-05-07

Applicant: Dawei Huang ,  Zuxu Qin ,  Drew G. Doblar ,  Waseem Ahmad ,  Dong Joon Yoon ,  Osman Javed

Inventor： Dawei Huang ,  Zuxu Qin ,  Drew G. Doblar ,  Waseem Ahmad ,  Dong Joon Yoon ,  Osman Javed

IPC: H04L7/00 ,  H04L27/06

CPC classification number: H04L7/0062

Abstract: An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

Abstract translation: 模拟波特率时钟和数据恢复装置包括第一跟踪和保持电路，其将接收到的信号延迟一个单位间隔以产生奇数信号; 第二轨道和保持电路，其将接收到的信号延迟一个单位间隔以产生均匀信号; 第一比较器电路; 和第二比较器电路。 第一跟踪和保持电路将奇数信号输出到第一比较器电路和第二比较器电路。 第二跟踪和保持电路将偶信号输出到第一比较器电路和第二比较器电路。 第一个比较器将奇数信号加到偶数信号，并输出第一个电位定时误差。 第二比较器减去奇数信号和偶数信号，并输出第二电位定时误差信号。 从第一和第二电位定时误差信号导出期望的定时误差信号。 所需的定时误差信号用于确定信号采样是早还是晚。