公开(公告)号：US20050280468A1

公开(公告)日：2005-12-22

申请号：US10975107

申请日：2004-10-28

申请人： Jungwoo Song

发明人： Jungwoo Song

IPC分类号： H03F1/30 ,  H03F3/18 ,  H03F3/30 ,  H03F3/345

CPC分类号： H03F3/30 ,  H03F1/301 ,  H03F3/3022 ,  H03F3/345

摘要： Provided is an amplifier including a system for controlling output stage quiescent current. The amplifier includes a driving stage including first pmos and nmos transistors coupled together, and an output stage connected to the driving stage. The output stage includes second pmos and nmos transistors coupled together. The amplifier also includes a quiescent control stage connected to the driving stage and including third pmos and nmos transistors coupled together, fourth pmos coupled to third pmos and 4th nmos coupled to 3rd nmos. A topology of the coupled third pmos and nmos transistors substantially matches a topology of the coupled first pmos and nmos transistors, and 4th pmos and nmos match to 2nd pmos and nmos.

摘要翻译： 提供了一种包括用于控制输出级静态电流的系统的放大器。 放大器包括驱动级，其包括耦合在一起的第一pmos和nmos晶体管，以及连接到驱动级的输出级。 输出级包括耦合在一起的第二pmos和nmos晶体管。 放大器还包括连接到驱动级的静态控制级，并且包括耦合在一起的第三pmos和nmos晶体管，耦合到第三薄膜晶体管的第四薄膜和耦合到第三薄膜晶体管的第四薄膜 > nmos。 耦合的第三pmos和nmos晶体管的拓扑结构基本上匹配耦合的第一pmos和nmos晶体管的拓扑，并且第4个pmos和nmos匹配到第2个pmos和nmos。

公开(公告)号：US20050179574A1

公开(公告)日：2005-08-18

申请号：US11031071

申请日：2005-01-10

申请人： Minsheng Wang ,  Jungwoo Song

发明人： Minsheng Wang ,  Jungwoo Song

IPC分类号： H03M3/00 ,  H03M7/32

CPC分类号： H03M7/3042

摘要： Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.

摘要翻译： 提供了一种用于实现多速率模拟有限脉冲响应（FIR）滤波器的系统和方法。 本发明的系统包括具有第一加法器和量化器的调制器。 第一加法器包括输出端口，并且量化器包括（i）耦合到第一加法器输出端口的输入端口和（ii）量化器输出端口。 还包括第二加法器，具有耦合到第一加法器输出端口的一个输入端口和耦合到量化器输出端口的另一个输入端口。 还包括至少两个两单元延迟，两单元延迟中的第一个具有耦合到第二加法器的输出端口的输入端口，以及耦合到两单元中的第二个单元的输入端口的输出端口 延误 第二两单元延迟的输出端口耦合到第一加法器的第一输入端口。

公开(公告)号：US08334721B2

公开(公告)日：2012-12-18

申请号：US13226233

申请日：2011-09-06

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F1/14

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US08212612B2

公开(公告)日：2012-07-03

申请号：US12804318

申请日：2010-07-19

申请人： Jungwoo Song ,  Xicheng Jiang ,  Minsheng Wang ,  Todd L. Brooks

发明人： Jungwoo Song ,  Xicheng Jiang ,  Minsheng Wang ,  Todd L. Brooks

IPC分类号： H03F3/38 ,  H03F3/217

CPC分类号： H03F3/217

摘要： Disclosed is a closed-loop class-D amplifier circuit including a modulated reference signal generator that provides a modulated reference signal in a feed-forward path, where the reference signal is modulated corresponding to an input signal. The closed-loop class-D amplifier circuit further includes a comparator to generate a control signal based on a comparison of the modulated reference signal and a correction signal, which in turn is produced by filtering a combination of the input signal and a feedback signal. The closed-loop class-D amplifier circuit also includes a pulse generator to generate a pulse-width-modulated signal to drive an output stage of the closed-loop class-D amplifier based on the control signal.

摘要翻译： 公开了一种闭环D类放大器电路，其包括在前馈路径中提供调制参考信号的调制参考信号发生器，其中参考信号根据输入信号被调制。 闭环D类放大器电路还包括比较器，用于基于调制参考信号和校正信号的比较产生控制信号，校正信号又通过滤波输入信号和反馈信号的组合来产生。 闭环D类放大器电路还包括脉冲发生器，以产生脉冲宽度调制信号，以根据控制信号驱动闭环D类放大器的输出级。

公开(公告)号：US20120025910A1

公开(公告)日：2012-02-02

申请号：US12804834

申请日：2010-07-29

申请人： Xicheng Jiang ,  Jungwoo Song ,  Minsheng Wang ,  Todd L. Brooks

发明人： Xicheng Jiang ,  Jungwoo Song ,  Minsheng Wang ,  Todd L. Brooks

IPC分类号： H03F3/217

CPC分类号： H03F3/217

摘要： Disclosed is a switching amplifier having an enhanced supply rejection. The switching amplifier comprises a digital modulator that provides a modulated signal. The switching amplifier further comprises a closed-loop analog driver that is coupled to the digital modulator. As disclosed, the closed-loop analog driver is configured to re-modulate a modulation signal that corresponds to the modulated signal. An output stage of the switching amplifier is driven by the re-modulated signal, thereby providing enhanced supply rejection. In one embodiment, the modulated signal is produced by a digital pulse-width modulator (PWM) circuit of a Class-D amplifier, and has a pulse rate substantially less than a clock rate of the digital PWM circuit. In one embodiment, the switching amplifier is implemented as an audio amplifier in a mobile communication device such as a cellular telephone.

公开(公告)号：US20120013402A1

公开(公告)日：2012-01-19

申请号：US12804318

申请日：2010-07-19

申请人： Jungwoo Song ,  Xicheng Jiang ,  Minsheng Wang ,  Todd L. Brooks

发明人： Jungwoo Song ,  Xicheng Jiang ,  Minsheng Wang ,  Todd L. Brooks

IPC分类号： H03F1/00

CPC分类号： H03F3/217

摘要： Disclosed is a closed-loop class-D amplifier circuit including a modulated reference signal generator that provides a modulated reference signal in a feed-forward path, where the reference signal is modulated corresponding to an input signal. The closed-loop class-D amplifier circuit further includes a comparator to generate a control signal based on a comparison of the modulated reference signal and a correction signal, which in turn is produced by filtering a combination of the input signal and a feedback signal. The closed-loop class-D amplifier circuit also includes a pulse generator to generate a pulse-width-modulated signal to drive an output stage of the closed-loop class-D amplifier based on the control signal.

摘要翻译： 公开了一种闭环D类放大器电路，其包括在前馈路径中提供调制参考信号的调制参考信号发生器，其中参考信号根据输入信号被调制。 闭环D类放大器电路还包括比较器，用于基于调制参考信号和校正信号的比较产生控制信号，校正信号又通过滤波输入信号和反馈信号的组合来产生。 闭环D类放大器电路还包括脉冲发生器，以产生脉冲宽度调制信号，以根据控制信号驱动闭环D类放大器的输出级。

公开(公告)号：US20110260793A1

公开(公告)日：2011-10-27

申请号：US12799598

申请日：2010-04-27

申请人： Xicheng Jiang ,  Jungwoo Song

发明人： Xicheng Jiang ,  Jungwoo Song

IPC分类号： H03F3/217

CPC分类号： H03F3/217

摘要： Disclosed is an amplifier circuit configured to amplify a pulse stream. The amplifier circuit comprises a switching block including a first switch operable to couple an output node of the switching block to a positive reference voltage, a second switch operable to couple the output node to a ground reference voltage and a third switch operable to couple the output node to a negative reference voltage. The amplifier circuit is configured to amplify the pulse stream into an amplified signal detectable at the output node such that the amplified signal has a common-mode voltage level substantially equal to zero volts. In one embodiment, the amplifier circuit is configured to amplify the pulse stream in accordance with a Class-D amplification scheme. In one embodiment, the output node can be directly connected to a load device without a DC blocking capacitor being interposed between the output node and the load device.

摘要翻译： 公开了一种被配置为放大脉冲流的放大器电路。 放大器电路包括切换块，其包括可操作以将切换块的输出节点耦合到正参考电压的第一开关，可操作以将输出节点耦合到接地参考电压的第二开关和可操作以将输出 节点到负参考电压。 放大器电路被配置为将脉冲流放大到在输出节点处可检测的放大信号，使得放大的信号具有基本上等于零伏特的共模电压电平。 在一个实施例中，放大器电路被配置为根据D类放大方案来放大脉冲流。 在一个实施例中，输出节点可以直接连接到负载装置，而不会在输出节点和负载装置之间插入直流阻塞电容器。

公开(公告)号：US20080069373A1

公开(公告)日：2008-03-20

申请号：US11523693

申请日：2006-09-20

申请人： Xicheng Jiang ,  Jungwoo Song ,  Jianlong Chen

发明人： Xicheng Jiang ,  Jungwoo Song ,  Jianlong Chen

IPC分类号： H04B15/00

CPC分类号： H04R3/04

摘要： A noise reduction circuit for reducing the effects of low frequency noise such as wind noise in communications applications is described. In one embodiment, the noise reduction circuit features a high pass filter formed by exploiting the existing off-chip AC coupling capacitances in making the connection to the source of audio signals. The filter may be adaptive to environmental low frequency noise level through programming the shunt resistances. A low-noise wide dynamic range programmable gain amplifier is also described. Adaptive equalization of the audio signal is also described through the utilization of programmable front-end resistors and a back-end audio equalizer.

摘要翻译： 描述了用于降低通信应用中诸如风噪声的低频噪声的影响的降噪电路。 在一个实施例中，噪声降低电路具有通过利用现有的片外AC耦合电容在形成与音频信号源的连接而形成的高通滤波器。 滤波器可以通过编程分流电阻来适应环境低频噪声电平。 还描述了低噪声宽动态范围可编程增益放大器。 还通过利用可编程前端电阻和后端音频均衡器来描述音频信号的自适应均衡。

公开(公告)号：US07304538B2

公开(公告)日：2007-12-04

申请号：US10975107

申请日：2004-10-28

申请人： Jungwoo Song

发明人： Jungwoo Song

IPC分类号： H03F3/185

CPC分类号： H03F3/30 ,  H03F1/301 ,  H03F3/3022 ,  H03F3/345

摘要： Provided is an amplifier including a system for controlling output stage quiescent current. The amplifier includes a driving stage including first pmos and nmos transistors coupled together, and an output stage connected to the driving stage. The output stage includes second pmos and nmos transistors coupled together. The amplifier also includes a quiescent control stage connected to the driving stage and including third pmos and nmos transistors coupled together, fourth pmos coupled to third pmos and 4th nmos coupled to 3rd nmos. A topology of the coupled third pmos and nmos transistors substantially matches a topology of the coupled first pmos and nmos transistors, and 4th pmos and nmos match to 2nd pmos and nmos.

摘要翻译： 提供了一种包括用于控制输出级静态电流的系统的放大器。 放大器包括驱动级，其包括耦合在一起的第一pmos和nmos晶体管，以及连接到驱动级的输出级。 输出级包括耦合在一起的第二pmos和nmos晶体管。 放大器还包括连接到驱动级的静态控制级，并且包括耦合在一起的第三pmos和nmos晶体管，耦合到第三薄膜晶体管的第四薄膜和耦合到第三薄膜晶体管的第四薄膜 > nmos。 耦合的第三pmos和nmos晶体管的拓扑结构基本上匹配耦合的第一pmos和nmos晶体管的拓扑，并且第4个pmos和nmos匹配到第2个pmos和nmos。

公开(公告)号：US06856267B1

公开(公告)日：2005-02-15

申请号：US10778193

申请日：2004-02-17

申请人： Minsheng Wang ,  Jungwoo Song

发明人： Minsheng Wang ,  Jungwoo Song

IPC分类号： H03M3/00 ,  H03M7/32

CPC分类号： H03M7/3042

摘要： Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.