公开(公告)号：US07298008B2

公开(公告)日：2007-11-20

申请号：US11275638

申请日：2006-01-20

申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

摘要： Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

摘要翻译： 公开了一种硅控制整流器，制造硅控制整流器的方法和使用硅控整流器作为集成电路的静电放电保护器件。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US08737028B2

公开(公告)日：2014-05-27

申请号：US13312047

申请日：2011-12-06

申请人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

发明人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

IPC分类号： H02H9/04 ,  G06F17/50

CPC分类号： H02H9/046

摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.

摘要翻译： 用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。 场效应晶体管与反相器的输出端相连。 响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。 响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。

公开(公告)号：US08637353B2

公开(公告)日：2014-01-28

申请号：US13013378

申请日：2011-01-25

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L21/82

CPC分类号： H01L22/30 ,  H01L21/76886 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  Y10T29/5313 ,  Y10T29/532 ,  H01L2924/00

摘要： Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

摘要翻译： 用于改变布线路径的电阻的方法和系统。 将布线路径的电阻与目标电阻值进行比较。 如果布线路径的电阻超过目标电阻值，则选择性地向布线路径施加电流，以物理地改变布线路径的一部分。 可以选择电流来改变布线路径，使得电阻下降到小于或等于目标电阻值的值。

公开(公告)号：US20130271883A1

公开(公告)日：2013-10-17

申请号：US13446394

申请日：2012-04-13

申请人： Shunhua Chang ,  James Paul Di Sarro ,  Robert J. Gauthier, JR. ,  Nathan Jack ,  Souvick Mitra

发明人： Shunhua Chang ,  James Paul Di Sarro ,  Robert J. Gauthier, JR. ,  Nathan Jack ,  Souvick Mitra

IPC分类号： H02H9/04

CPC分类号： G01R31/002 ,  G01R31/2851 ,  H01L27/0248 ,  H02H9/046 ,  H05K9/0067

摘要： A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.

摘要翻译： 提供了使用ESD测试系统在静电放电（ESD）测试期间保护集成电路内的器件的方法。 该方法包括将直流（DC）偏置电压施加到集成电路的至少一个器件的输入，并将ESD仿真信号施加到集成电路的至少一个其他输入。 施加的ESD模拟信号沿着第一电流路径传导到第一地，而与至少一个装置相关联的低电流信号沿着第二电流路径传导到第二地。 响应于由所施加的ESD模拟信号产生的第二接地上的信号变化，DC偏置电压在至少一个器件的输入和第二接地之间以基本恒定的值保持。

公开(公告)号：US08514535B2

公开(公告)日：2013-08-20

申请号：US12987276

申请日：2011-01-10

申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra

发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra

IPC分类号： H02H3/22

CPC分类号： H01L27/0285

摘要： Structures and methods for electrostatic discharge (ESD) device control in an integrated circuit are provided. An ESD protection structure includes an input/output (I/O) pad, and an ESD field effect transistor (FET) including a drain connected to the I/O pad, a source connected to ground, and a gate. A first control FET includes a drain connected to the I/O pad, a source connected to the gate of the ESD FET, and a gate connected to ground. A second control FET includes a drain connected to the gate of the ESD FET and the source of the first control FET, a source connected to ground, and a gate connected to the I/O pad.

摘要翻译： 提供集成电路中静电放电（ESD）器件控制的结构和方法。 ESD保护结构包括输入/​​输出（I / O）焊盘和包括连接到I / O焊盘的漏极，连接到地的源极和栅极的ESD场效应晶体管（FET）。 第一控制FET包括连接到I / O焊盘的漏极，连接到ESD FET的栅极的源极和连接到地的栅极。 第二控制FET包括连接到ESD FET的栅极和第一控制FET的源极的漏极，连接到地的源极和连接到I / O焊盘的栅极。

公开(公告)号：US08503140B2

公开(公告)日：2013-08-06

申请号：US12898013

申请日：2010-10-05

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/747 ,  H01L29/87 ,  H02H9/04

摘要： Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.

摘要翻译： 提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。 该器件包括对称双向背对背层叠可控硅整流器（SCR）。 背对背堆叠的SCR中的第一个的阳极连接到输入。 背对背堆叠的SCR的第二个的阳极连接到地面。 第一个和第二个背靠背堆叠的SCR的阴极连接在一起。 对称双向背靠背SCR中的每一个包括一对二极管，其引导电流朝向阴极，其在施加电压时有效地变得有效地反向偏置，并且从对称的双向后向SCR中的一个去激活元件， 另一个对称双向背对背SCR的二极管在与反向偏置二极管相同的方向上直流电流，反向SCR。

公开(公告)号：US20120187525A1

公开(公告)日：2012-07-26

申请号：US13012137

申请日：2011-01-24

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L29/12 ,  G06F17/50 ,  H01L21/36

CPC分类号： H01L27/0255 ,  G06F17/5022 ,  G06F17/5045 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/6609 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/861

摘要： Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

摘要翻译： 在SOI工艺中具有减小的结面积的器件结构，制造器件结构的方法以及横向二极管的设计结构。 器件结构包括位于器件区域中并与阳极和阴极之间的p-n结相交的一个或多个电介质区域，例如STI区域。 可以使用浅沟槽隔离技术形成的电介质区域用于在p-n结和阳极侧向间隔的位置处减小p-n结相对于阴极宽度区域的宽度。 介质区域的宽度差和存在产生不对称二极管结构。 由电介质区域占据的器件区域的体积被最小化以保持阴极和阳极的体积。

公开(公告)号：US08217455B2

公开(公告)日：2012-07-10

申请号：US12102032

申请日：2008-04-14

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/0248

摘要： Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region.

摘要翻译： 具有增强的静电放电保护的绝缘体上半导体器件结构以及具有增强的静电放电保护的器件结构的集成电路的设计结构。 一种器件形成在绝缘体上半导体衬底的器件层的体区中，该衬底由环形电介质填充的隔离结构的内周侧壁限定，该隔离结构从器件层的顶表面延伸到绝缘体 绝缘体上半导体衬底的层。 环形导电互连延伸穿过主体区域和绝缘层，以将体区域与绝缘体上半导体衬底的体晶片连接。 环形导电互连件设置在隔离结构的内周侧壁的内侧，环形环绕主体区域。

公开(公告)号：US08101505B2

公开(公告)日：2012-01-24

申请号：US12135242

申请日：2008-06-09

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

IPC分类号： H01L21/479 ,  H01L23/52

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.

摘要翻译： 本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由 阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。 通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

公开(公告)号：US07956671B2

公开(公告)日：2011-06-07

申请号：US12496002

申请日：2009-07-01

申请人： Michel J. Abou-Khalil ,  Tom C. Lee ,  Junjun Li ,  Robert J. Gauthier, Jr. ,  Christopher S. Putnam ,  Souvick Mitra

发明人： Michel J. Abou-Khalil ,  Tom C. Lee ,  Junjun Li ,  Robert J. Gauthier, Jr. ,  Christopher S. Putnam ,  Souvick Mitra

IPC分类号： H01L23/52

CPC分类号： G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

摘要翻译： 在电熔丝编程/重新编程电路的一个实施例中，电熔丝具有位于长低的原子扩散电阻较长的导体层的相对侧和同一端的两个短的高原子扩散电阻的导体层。 电压源用于改变施加到端子的电压的极性和可选的电压大小，以便控制长导体层内电子的双向流动，从而在长导体上形成开路和/或短路 层 - 短导体层接口。 可以使用这种打开和/或短路的形成来实现不同的编程状态。 其他电路结构实施例包括具有附加导体层和附加端子的电子保险丝，以便允许甚至更多的编程状态。 还公开了相关联的电熔丝编程和重新编程方法的实施例。