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    RC-triggered ESD clamp device with feedback for time constant adjustment
    1.
    发明授权
    RC-triggered ESD clamp device with feedback for time constant adjustment 有权
    RC触发ESD钳位装置，具有时间常数调整反馈

    公开(公告)号：US08737028B2

    公开(公告)日：2014-05-27

    申请号：US13312047

    申请日：2011-12-06

    申请人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

    发明人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

    IPC分类号： H02H9/04 ,  G06F17/50

    CPC分类号： H02H9/046

    摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.

    摘要翻译： 用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。 场效应晶体管与反相器的输出端相连。 响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。 响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。

    Non-planar capacitor and method of forming the non-planar capacitor
    2.
    发明授权
    Non-planar capacitor and method of forming the non-planar capacitor 有权
    非平面电容器和非平面电容器的形成方法

    公开(公告)号：US08610249B2

    公开(公告)日：2013-12-17

    申请号：US13434964

    申请日：2012-03-30

    申请人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H01L21/02

    CPC分类号： H01L27/0805 ,  H01L21/845 ,  H01L27/1211 ,  H01L28/90 ,  H01L29/94

    摘要： Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing.

    摘要翻译： 这里公开了非平面电容器的实施例。 非平面电容器可以包括在半导体衬底上方的多个鳍片。 每个翅片可以包括半导体衬底上的至少绝缘体部分和在绝缘体部分上方堆叠具有基本上均匀的导电性的半导体部分。 门结构可以穿过翅片的中心部分。 该栅极结构可以包括在电介质层上的共形介电层和导体层（例如，覆盖层或保形导体层）。 这种非平面电容器可以在导体层和散热片之间展现可选地可调谐的第一电容和导体层与半导体衬底之间的第二电容。 本文还公开了可用于形成这种非平面电容器并且与现有技术的多栅极非平面场效应晶体管（MUGFET）处理兼容的方法实施例。

    Gate dielectric breakdown protection during ESD events
    3.
    发明授权
    Gate dielectric breakdown protection during ESD events 有权
    ESD事件期间的栅极绝缘击穿保护

    公开(公告)号：US08634174B2

    公开(公告)日：2014-01-21

    申请号：US13115492

    申请日：2011-05-25

    申请人： Michel J. Abou-Khalil ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Yang Yang

    发明人： Michel J. Abou-Khalil ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Yang Yang

    IPC分类号： H02H9/00 ,  H02H3/22

    CPC分类号： H02H9/046 ,  G06F17/5063 ,  H01L27/0285

    摘要： Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.

    摘要翻译： 用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。 保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。 在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。 保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。 保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。 或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。

    RC-triggered semiconductor controlled rectifier for ESD protection of signal pads
    4.
    发明授权
    RC-triggered semiconductor controlled rectifier for ESD protection of signal pads 有权
    RC触发半导体可控整流器用于信号焊盘的ESD保护

    公开(公告)号：US08891212B2

    公开(公告)日：2014-11-18

    申请号：US13079946

    申请日：2011-04-05

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H02H9/04 ,  H03K19/003 ,  H01L27/02

    CPC分类号： H02H9/046 ,  H01L27/0262 ,  H03K19/00361 ,  Y10T29/49002

    摘要： RC-trigger circuits for a semiconductor controlled rectifier (SCR), methods of providing electrostatic discharge (ESD) protection, and design structures for a RC-trigger circuit. The RC-trigger circuit is coupled to an input/output (I/O) signal pad by an isolation diode and is coupled to a power supply voltage by a power supply diode. Under normal operating conditions, the isolation diode is reverse biased, isolating the RC-trigger circuit from the input/output (I/O) pad, and the power supply diode is forward biased so that the RC-trigger circuit is supplied with power. The isolation diode may become forward biased during ESD events while the chip is unpowered, causing the RC-trigger circuit to trigger an SCR configured protect the signal pad from ESD into a conductive state. The power supply diode may become reverse biased during the ESD event, which isolates the power supply rail from the ESD voltage pulse.

    摘要翻译： 用于半导体可控整流器（SCR）的RC触发电路，提供静电放电（ESD）保护的方法以及用于RC触发电路的设计结构。 RC触发电路通过隔离二极管耦合到输入/输出（I / O）信号焊盘，并通过电源二极管耦合到电源电压。 在正常工作条件下，隔离二极管反向偏置，将RC触发电路与输入/输出（I / O）焊盘隔离，电源二极管正向偏置，使RC触发电路供电。 在ESD事件期间，隔离二极管可能会在芯片未上电时产生正向偏置，导致RC触发电路触发SCR配置，从而将信号焊盘从ESD保护到导通状态。 在ESD事件期间，电源二极管可能会反向偏置，从而将电源轨与ESD电压脉冲隔离。

    Design structures for high-voltage integrated circuits
    5.
    发明授权
    Design structures for high-voltage integrated circuits 失效
    高压集成电路的设计结构

    公开(公告)号：US07786535B2

    公开(公告)日：2010-08-31

    申请号：US12059034

    申请日：2008-03-31

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    IPC分类号： H01L29/78

    CPC分类号： H01L27/1203

    摘要： Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.

    摘要翻译： 高压集成电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的设计结构可以包括具有位于第一和第二栅电极之间的半导体本体的器件结构。 第一和第二栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将第一和第二栅极电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，介电材料可与形成其它器件隔离区的工艺同时进行。

    Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures
    8.
    发明授权
    Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures 有权
    用于高压引脚ESD保护的双向背对背堆叠SCR，制造和设计结构的方法

    公开(公告)号：US08503140B2

    公开(公告)日：2013-08-06

    申请号：US12898013

    申请日：2010-10-05

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0262 ,  H01L29/747 ,  H01L29/87 ,  H02H9/04

    摘要： Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.

    摘要翻译： 提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。 该器件包括对称双向背对背层叠可控硅整流器（SCR）。 背对背堆叠的SCR中的第一个的阳极连接到输入。 背对背堆叠的SCR的第二个的阳极连接到地面。 第一个和第二个背靠背堆叠的SCR的阴极连接在一起。 对称双向背靠背SCR中的每一个包括一对二极管，其引导电流朝向阴极，其在施加电压时有效地变得有效地反向偏置，并且从对称的双向后向SCR中的一个去激活元件， 另一个对称双向背对背SCR的二极管在与反向偏置二极管相同的方向上直流电流，反向SCR。

    Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures
    9.
    发明授权
    Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures 有权
    具有用于增强静电放电保护的体对衬底连接的绝缘体上半导体器件结构以及这种绝缘体上半导体器件结构的设计结构

    公开(公告)号：US08217455B2

    公开(公告)日：2012-07-10

    申请号：US12102032

    申请日：2008-04-14

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L27/0248

    摘要： Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region.

    摘要翻译： 具有增强的静电放电保护的绝缘体上半导体器件结构以及具有增强的静电放电保护的器件结构的集成电路的设计结构。 一种器件形成在绝缘体上半导体衬底的器件层的体区中，该衬底由环形电介质填充的隔离结构的内周侧壁限定，该隔离结构从器件层的顶表面延伸到绝缘体 绝缘体上半导体衬底的层。 环形导电互连延伸穿过主体区域和绝缘层，以将体区域与绝缘体上半导体衬底的体晶片连接。 环形导电互连件设置在隔离结构的内周侧壁的内侧，环形环绕主体区域。