公开(公告)号：US4321695A

公开(公告)日：1982-03-23

申请号：US97106

申请日：1979-11-23

Applicant: Donald J. Redwine ,  Lionel S. White, Jr.

Inventor： Donald J. Redwine ,  Lionel S. White, Jr.

IPC: G11C7/10 ,  G11C8/04 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/40

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C7/1036 ,  G11C8/04

Abstract: A semiconductor memory device of the single-chip MOS/LSI one-transistor dynamic RAM cell array type stores both data and address in rows of the array and uses a high speed serial access shift register as its data input/output system. The serial shift register has a number of stages equal to the number of columns in the memory cell array, and data in the shift register is transferred into or out of the columns of the array when a comparator indicates that an address input matches the stored row address. The rows are sequentially activated by a commutator, so no row or column decoders are needed. The device may be made fault tolerant by use of an electrically programmable floating gate transistor connected to each row, and programming this transistor to blank input or output if the row includes bad cells. The fault tolerant feature is transparent to the computer system using the memory.

Abstract translation: 单芯片MOS / LSI单晶体管动态RAM单元阵列类型的半导体存储器件存储阵列中的数据和地址，并且使用高速串行访问移位寄存器作为其数据输入/输出系统。 串行移位寄存器具有与存储单元阵列中的列数相等的级数，并且当比较器指示地址输入与存储行相匹配时，移位寄存器中的数据被传送到阵列的列或数组的列中 地址。 这些行由换向器依次激活，因此不需要行或列解码器。 该器件可以通过使用连接到每一行的电可编程浮栅晶体管来实现容错，并且如果该行包含不良单元，则将该晶体管编程为空输入或输出。 容错功能对于使用内存的计算机系统是透明的。

公开(公告)号：US07385840B2

公开(公告)日：2008-06-10

申请号：US11191348

申请日：2005-07-28

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: An SRAM memory cell structure utilizing a read driver transistor and a column select write transistor, and a method of operating the same. The SRAM memory cell comprises first and second cross-coupled inverters, having a first and second latch nodes, respectively. The cell further comprises a first write pass transistor connected between the first latch node of the first inverter and a first pass node, and a first wordline pass transistor connected between the first pass node and a first bitline. The cell also includes a first read driver connected between the first pass node and a source potential, and a control terminal of the first read driver connected to the second latch node of the second inverter.

Abstract translation: 利用读驱动晶体管和列选择写晶体管的SRAM存储单元结构及其操作方法。 SRAM存储单元包括分别具有第一和第二锁存节点的第一和第二交叉耦合的反相器。 该单元还包括连接在第一反相器的第一锁存节点和第一通过节点之间的第一写入通道晶体管，以及连接在第一通过节点和第一位线之间的第一字线传输晶体管。 该单元还包括连接在第一通过节点和源极电位之间的第一读取驱动器，以及连接到第二反相器的第二锁存器节点的第一读取驱动器的控制端子。

公开(公告)号：US5345422A

公开(公告)日：1994-09-06

申请号：US57589

申请日：1993-05-06

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C5/143

Abstract: A circuit for producing a power up detection signal for use in, and being integrated onto the same semiconductor substrate as a dynamic memory device is disclosed. The circuit has a first node and a circuit to promote a low voltage on the first node when a voltage obtained from a supply voltage applied to the dynamic memory is below a predetermined level. It has a second node from which the power up detection signal can be removed. Included is a circuit to promote the obtained voltage on said second node when the obtained voltage is below the predetermined level, whereby the power up detection signal can be used to isolate the obtained voltage from the dynamic memory device. Included is a circuit to maintain a high voltage on the first node when the obtained voltage exceeds the predetermined level. Also included is a circuit to maintain the voltage on the second node at a low state when the high voltage appears on the first node, whereby the power up detection signal can be used to apply to obtained voltage to said dynamic memory device.

Abstract translation: 公开了一种用于产生用于动态存储器件并集成到同一半导体衬底上的上电检测信号的电路。 当从施加到动态存储器的电源电压获得的电压低于预定电平时，电路具有第一节点和电路，以在第一节点上促进低电压。 它具有第二节点，可以从其中去除上电检测信号。 包括当获得的电压低于预定电平时促进所述第二节点上获得的电压的电路，由此可以使用上电检测信号来将获得的电压与动态存储器件隔离。 包括当所获得的电压超过预定电平时在第一节点上保持高电压的电路。 还包括当高电压出现在第一节点上时，将第二节点上的电压维持在低状态的电路，由此可以使用上电检测信号将所获得的电压应用于所述动态存储器件。

公开(公告)号：US5321291A

公开(公告)日：1994-06-14

申请号：US68731

申请日：1993-05-26

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7831

Abstract: A power MOSFET device formed in a face of a semiconductor layer of a first conductivity type is provided. A first, second and third source region of a second conductivity type are formed in the face of the semiconductor layer within a moat and adjacent to its edges. A source conductor is insulatively disposed adjacent the face of the semiconductor layer and contacts the first, second and third source regions at a plurality of locations. A first and second drain region of a second conductivity type is also formed in the face of the semiconductor layer disposed spaced from and between the first and second source regions and the second and third source regions, respectively. A drain conductor is insulatively disposed adjacent the face of the semiconductor layer and contacts the first and second drain regions at a plurality of locations. A first and second field plate are insulatively disposed adjacent the face of the semiconductor layer and substantially adjacent and surrounding the first and second drain regions respectively. A first, second, third and fourth prongs forming gates of the device are insulatively disposed adjacent the face of the semiconductor layer and between the first field plate and the first and second source regions and between the second field plate and the second and third source regions. A portion of each of the gate prongs is disposed substantially above a portion of the first and second field plates. Conductive contacts connect the first and second field plates and the first and second drain regions.

Abstract translation: 提供了形成在第一导电类型的半导体层的表面上的功率MOSFET器件。 第二导电类型的第一，第二和第三源极区域形成在护城河内并且与其边缘相邻的半导体层的表面。 源极导体邻近半导体层的表面绝缘地设置并且在多个位置处接触第一，第二和第三源极区域。 第二导电类型的第一和第二漏极区域也分别形成在与第一和第二源极区域以及第二和第三源极区域之间隔开并位于其间的半导体层的表面上。 漏极导体邻近半导体层的表面绝缘地设置并且在多个位置处接触第一和第二漏极区域。 第一和第二场板被绝缘地布置成邻近半导体层的表面并且分别基本相邻并围绕第一和第二漏极区域。 形成器件的栅极的第一，第二，第三和第四尖端邻近半导体层的表面并且在第一场板与第一和第二源极区之间以及第二场板与第二和第三源极区之间 。 每个栅极插脚的一部分基本上设置在第一和第二场板的一部分上方。 导电触头连接第一和第二场板以及第一和第二漏极区域。

公开(公告)号：US5008214A

公开(公告)日：1991-04-16

申请号：US384858

申请日：1989-07-21

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L29/945 ,  H01L27/10841

Abstract: A dynamic random access memory cell array is disclosed which has storage capacitors and access transistors formed on the sidewalls of pillars created by trenches etched into the face of a semiconductor bar. A storage capacitor for a cell uses the sidewalls of the pillar as one plate and a polysilicon plug or web as the other plate. The channel of each access transistor is formed in the upper part of the sidewall of only a portion of the pillar, using an upper edge of the capacitor region as the source region of the transistor and having an N+ drain region at the top of the pillar. A cross-point array is made possible by merging two adjacent wordlines as a pair of overlying conductor strips extending along the face over the trenches, between pillars, and forming the transistor gates by alternate protrusions from these strips, extending down into the trenches at the channel area.

Abstract translation: 公开了一种动态随机存取存储单元阵列，其具有存储电容器和形成在由蚀刻到半导体棒的表面中的沟槽产生的柱的侧壁上的存取晶体管。 用于电池的存储电容器使用柱的侧壁作为一个板，并且将多晶硅插塞或幅材用作另一个板。 每个存取晶体管的沟道形成在只有一部分柱的侧壁的上部，使用电容器区的上边缘作为晶体管的源极区，并且在柱的顶部具有N +漏极区 。 通过将两个相邻的字线合并成一对上覆导体条，跨越沟槽，在柱之间延伸的一对上覆导体条，并且通过来自这些条的交替突起从这些条形成晶体管栅极，向下延伸到沟槽中，从而形成交叉点阵列 渠道区域。

公开(公告)号：US4926224A

公开(公告)日：1990-05-15

申请号：US319923

申请日：1989-03-06

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10841 ,  H01L29/945 ,  Y10S257/922 ,  Y10S257/929

Abstract: A dynamic random access memory cell array is disclosed which has storage capacitors and access transistors formed on the sidewalls of pillars created by trenches etched into the face of a semiconductor bar. A storage capacitor for a cell uses the sidewalls of the pillar as one plate and a polysilicon plug or web as the other plate. The channel of each access transistor is formed in the upper part of the sidewall of only a portion of the pillar, using an upper edge of the capacitor region as the source region of the transistor and having an N+ drain region at the top of the pillar. A cross-point array is made possible by merging two adjacent wordlines as a pair of overlying conductor strips extending along the face over the trenches, between pillars, and forming the transistor gates by alternate protrusions from these strips, extending down into the trenches at the channel area.

Abstract translation: 公开了一种动态随机存取存储单元阵列，其具有存储电容器和形成在由蚀刻到半导体棒的表面中的沟槽产生的柱的侧壁上的存取晶体管。 用于电池的存储电容器使用柱的侧壁作为一个板，并且将多晶硅插塞或幅材用作另一个板。 每个存取晶体管的沟道形成在只有一部分柱的侧壁的上部，使用电容器区的上边缘作为晶体管的源极区，并且在柱的顶部具有N +漏极区 。 通过将两个相邻的字线合并成一对上覆导体条，跨越沟槽，在柱之间延伸的一对上覆导体条，并且通过来自这些条的交替突起从这些条形成晶体管栅极，向下延伸到沟槽中，从而形成交叉点阵列 渠道区域。

公开(公告)号：US4897818A

公开(公告)日：1990-01-30

申请号：US64290

申请日：1987-06-18

Applicant: Donald J. Redwine ,  Raymond Pinkham

Inventor： Donald J. Redwine ,  Raymond Pinkham

IPC: G09G5/02 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G11C7/10 ,  H04N5/907

CPC classification number: G09G5/363 ,  G09G5/39 ,  G11C7/1075 ,  H04N5/907 ,  G09G2360/126 ,  G09G5/022 ,  G09G5/393

Abstract: In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

Abstract translation: 在具有并入移位寄存器的双端口位映射RAM单元的视频计算机系统中，提供用于在列线和移位寄存器之间耦合数据，并且同时防止任何列线与随机数据输出端 RAM单元。 因此，这防止了来自RAM单元的两个或更多个不同的数据位同时出现并引起混淆，即哪个是有效信号，哪个是杂散信号。

公开(公告)号：US4747081A

公开(公告)日：1988-05-24

申请号：US567110

申请日：1983-12-30

Applicant: Andrew Heilveil ,  Jerry R. VanAken ,  Karl M. Guttag ,  Donald J. Redwine ,  Raymond Pinkham ,  Mark F. Novak

Inventor： Andrew Heilveil ,  Jerry R. VanAken ,  Karl M. Guttag ,  Donald J. Redwine ,  Raymond Pinkham ,  Mark F. Novak

IPC: G11C7/10 ,  H04N5/907 ,  G11C8/00

CPC classification number: G11C7/1075 ,  H04N5/907

Abstract: In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, column address to the RAM unit is also used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the shift register containing only the data bits of interest.

Abstract translation: 在视频型计算机系统等中，提供了一种改进的存储器电路，用于使系统适应具有不同分辨率的CRT屏幕。 存储器电路包括具有足够的单元以适应任何想要使用的CRT屏幕的位映射RAM单元或芯片，以及具有与RAM单元中的不同列单元对应的多个不同位置的抽头的移位寄存器。 当RAM单元处于串行模式时，RAM单元的列地址也用于指示和启动适当的解码器电路以选择适于卸载仅包含感兴趣的数据位的移位寄存器的部分的分接头。

公开(公告)号：US4322635A

公开(公告)日：1982-03-30

申请号：US96723

申请日：1979-11-23

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: G11C11/4096 ,  G11C19/18 ,  G11C19/28

CPC classification number: G11C11/4096 ,  G11C19/184

Abstract: A semiconductor device of the MOS/LSI type uses a high speed serial shift register in its input/output system. In a memory device, the serial shift register has a number of stages equal to the number of columns in the memory cell array and is split into two half registers connected to opposite sides of the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. For a write operation, data from external is loaded serially into the shift register, alternating bit by bit between the two half registers. For a read operation, data is serially shifted out of the register to external, again alternating between the half registers. The data register can be advanced at twice the clock frequency.

Abstract translation: MOS / LSI型的半导体器件在其输入/输出系统中使用高速串行移位寄存器。 在存储器件中，串行移位寄存器具有等于存储单元阵列中的列数的级数，并且通过传输门被分成连接到列的相对侧的两个半寄存器。 寄存器中的位可以被加载到阵列的列中，并且因此被加载到寻址的单元行，或者一个整个寻址的单元行的数据可以经由列和传送门被加载到移位寄存器级。 对于写操作，来自外部的数据被串行地加载到移位寄存器中，在两个半寄存器之间逐位交替。 对于读操作，数据从寄存器中串行移出到外部，再次在半寄存器之间交替。 数据寄存器可以以两倍的时钟频率进行。

公开(公告)号：US4239990A

公开(公告)日：1980-12-16

申请号：US940221

申请日：1978-09-07

Applicant: Ngai H. Hong ,  Edmund A. Reese ,  Donald J. Redwine

Inventor： Ngai H. Hong ,  Edmund A. Reese ,  Donald J. Redwine

IPC: G11C11/404 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  H01L27/108 ,  H03K3/356 ,  H03K5/135 ,  H03K17/16 ,  H03K17/284

CPC classification number: H03K3/356017 ,  G11C11/404 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  H01L27/108

Abstract: A clock generator for producing internal waveforms for an MOS dynamic RAM or the like provides a preselected delay period between input and output clocks. A pair-delay circuit including two transistor stages produces the desired delay, a driver circuit provides the necessary high level output. A pair of series transistors in the output of the pair-delay, with the node between the series transistors being precharged, provides precise control of the delay over a wide range. Power dissipation is reduced in the driver circuit by avoiding the possibility of d.c. current paths when the reset clock goes high.

Abstract translation: 用于产生用于MOS动态RAM等的内部波形的时钟发生器在输入和输出时钟之间提供预选的延迟时段。 包括两个晶体管级的对延迟电路产生期望的延迟，驱动电路提供必要的高电平输出。 在对延迟的输出中，串联晶体管之间的节点被预充电的一对串联晶体管提供了在宽范围内的延迟的精确控制。 通过避免直流电源的可能性，驱动电路中的功耗降低。 当复位时钟变高时，电流通路。