公开(公告)号：US06990035B2

公开(公告)日：2006-01-24

申请号：US10727888

申请日：2003-12-03

Applicant: Donald J. Redwine ,  Robert R. Doering

Inventor： Donald J. Redwine ,  Robert R. Doering

IPC: G11C7/00

CPC classification number: G11C11/417

Abstract: A method of operating a memory circuit to reduce standby current is disclosed. The method includes applying a first voltage (Vdd) to a power terminal (224) of a memory cell having a first (612) and a second (614) data terminal. A data bit is stored in a memory cell (600,602,604,606). A second voltage (VDA) different from the first voltage is applied to the power terminal. A third voltage (Ground) is applied to the first and second data terminals. The first voltage is applied to the power terminal.

Abstract translation: 公开了一种操作存储电路以减少待机电流的方法。 该方法包括将第一电压（Vdd）应用于具有第一（612）和第二（614）数据端的存储单元的电源端子（224）。 数据位存储在存储单元（600,602,604,606）中。 与第一电压不同的第二电压（VDA）被施加到电源端子。 第三电压（Ground）被施加到第一和第二数据端子。 第一个电压被施加到电源端子。

公开(公告)号：US5210639A

公开(公告)日：1993-05-11

申请号：US870721

申请日：1992-04-10

Applicant: Donald J. Redwine ,  Raymond Pinkham

Inventor： Donald J. Redwine ,  Raymond Pinkham

IPC: G09G5/36 ,  G09G5/39 ,  G09G5/391 ,  G09G5/395 ,  G11C7/10 ,  H04N5/907

CPC classification number: G09G5/391 ,  G09G5/363 ,  G09G5/395 ,  G11C7/1075 ,  H04N5/907 ,  G09G2360/126 ,  G09G2360/127

Abstract: In a video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

Abstract translation: 在具有并入了移位寄存器的双端口位映射RAM单元的视频计算机系统中，提供用于在列线和移位寄存器之间耦合数据，并且同时防止任何列线与随机数据输出端子耦合 的RAM单元。 因此，这防止了来自RAM单元的两个或更多个不同的数据位同时出现并引起混淆，即哪个是有效信号，哪个是杂散信号。

公开(公告)号：US5163024A

公开(公告)日：1992-11-10

申请号：US520986

申请日：1990-05-09

Applicant: Andrew L. Heilveil ,  Jerry R. VanAken ,  Karl M. Guttag ,  Donald J. Redwine ,  Raymond Pinkham ,  Mark F. Novak

Inventor： Andrew L. Heilveil ,  Jerry R. VanAken ,  Karl M. Guttag ,  Donald J. Redwine ,  Raymond Pinkham ,  Mark F. Novak

IPC: G11C7/10 ,  H04N5/907

CPC classification number: G11C7/1075 ,  H04N5/907

Abstract: In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a serial shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, a row of data is transferred into the serial shift register. Then the column address applied to the RAM unit is used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the serial shift register containing the data bits of interest.

Abstract translation: 在视频型计算机系统等中，提供了一种改进的存储器电路，用于使系统适应具有不同分辨率的CRT屏幕。 存储器电路包括具有足够的单元以适应任何想要使用的CRT屏幕的位映射RAM单元或芯片，以及具有对应于RAM单元中的不同列单元的多个不同位置的抽头的串行移位寄存器。 当RAM单元处于串行模式时，一行数据被传送到串行移位寄存器。 然后，应用于RAM单元的列地址用于指示和启动适当的解码器电路以选择适于卸载包含感兴趣的数据位的串行移位寄存器的部分的抽头。

公开(公告)号：US4081701A

公开(公告)日：1978-03-28

申请号：US691735

申请日：1976-06-01

Applicant: Lionel S. White, Jr. ,  Hugh P. McAdams ,  Donald J. Redwine

Inventor： Lionel S. White, Jr. ,  Hugh P. McAdams ,  Donald J. Redwine

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  H03K5/20 ,  G11C11/40 ,  H03K3/286 ,  H03K5/18

CPC classification number: G11C11/408 ,  G11C11/4091 ,  G11C11/4093

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. The load transistors in each bistable circuit have clock voltages applied to their gates after an initial sensing period, so the initial sensing is done without loads for the bistable circuit. After this initial period, the load transistors are turned on by boosting capacitors. Then, fixed biased transistors shunting the gates of the load device to the digit lines function to turn off the load device on the zero logic level side.

Abstract translation: MOS集成电路类型的随机存取存储器件采用在每列的中心具有双稳态读出放大器电路的单晶体管存储单元的行和列阵列。 每个双稳态电路中的负载晶体管在初始感测周期之后具有施加到其栅极的时钟电压，因此初始感测在双稳态电路的负载下完成。 在该初始时段之后，负载晶体管通过升压电容器导通。 然后，将负载装置的栅极分流到数字线的固定偏压晶体管起到关闭零逻辑电平侧的负载装置的作用。

公开(公告)号：US4689741A

公开(公告)日：1987-08-25

申请号：US567039

申请日：1983-12-30

Applicant: Donald J. Redwine ,  Raymond Pinkham

Inventor： Donald J. Redwine ,  Raymond Pinkham

IPC: G09G5/39 ,  G11C7/10 ,  H04N5/907 ,  G11C7/00 ,  G11C19/00

CPC classification number: H04N5/907 ,  G09G5/39 ,  G11C7/1075 ,  G09G2360/123 ,  G09G2360/126

Abstract: In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

Abstract translation: 在具有并入移位寄存器的双端口位映射RAM单元的视频计算机系统中，提供用于在列线和移位寄存器之间耦合数据，并且同时防止任何列线与随机数据输出端 RAM单元。 因此，这防止了来自RAM单元的两个或更多个不同的数据位同时出现并引起混淆，即哪个是有效信号，哪个是杂散信号。

公开(公告)号：US4639890A

公开(公告)日：1987-01-27

申请号：US567040

申请日：1983-12-30

Applicant: Andrew Heilveil ,  Jerry R. VanAken ,  Karl M. Guttag ,  Donald J. Redwine ,  Raymond Pinkham ,  Mark F. Novak

Inventor： Andrew Heilveil ,  Jerry R. VanAken ,  Karl M. Guttag ,  Donald J. Redwine ,  Raymond Pinkham ,  Mark F. Novak

IPC: G09G5/391 ,  G09G1/02

CPC classification number: G09G5/391

Abstract: In a computer system, an improved memory circuit is provided for accomodating video display circuits with CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accomodate any CRT screen intended to be used, and it further includes a serial shift register having a plurality of taps at locations corresponding to different preselected columns of cells in the chip. In the system, provision is included for selecting taps to unload only the portion of the shift register containing the bits of interest, whereby unused portions of the chip may be effectively excluded and the time for transferring data of interest to the CRT screen is reduced.

Abstract translation: 在计算机系统中，提供了一种改进的存储器电路，用于容纳具有不同分辨率的CRT屏幕的视频显示电路。 存储器电路包括具有足够的单元以容纳要使用的任何CRT屏幕的位映射RAM单元或芯片，并且还包括串行移位寄存器，其具有对应于芯片中的不同预选列单元格的位置处的多个抽头 。 在系统中，包括用于选择抽头以仅卸载包含感兴趣的位的移位寄存器的部分的提供，由此可以有效地排除芯片的未使用部分，并且将感兴趣的数据传送到CRT屏幕的时间减少。

公开(公告)号：US4281401A

公开(公告)日：1981-07-28

申请号：US96957

申请日：1979-11-23

Applicant: Donald J. Redwine ,  Lionel S. White, Jr. ,  G. R. Mohan Rao

Inventor： Donald J. Redwine ,  Lionel S. White, Jr. ,  G. R. Mohan Rao

IPC: G11C8/04 ,  G11C11/4096 ,  G11C11/40

CPC classification number: G11C8/04 ,  G11C11/4096

Abstract: A semiconductor memory device of the MOS/LSI type using an array of dynamic one-transistor cells has a high speed serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is split into two half registers connected to opposite sides of the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. For a write operation, data from external is loaded serially into the shift register, alternating bit by bit between the two half registers. For a read operation, data is serially shifted out of the register to external, again alternating between the half registers. The data register can be advanced at twice the clock frequency. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.

Abstract translation: 使用动态单晶体管单元阵列的MOS / LSI型半导体存储器件具有高速串行输入/输出系统。 具有等于​​存储单元阵列中的列数的级数的串行移位寄存器被分离成通过传输门连接到列的相对侧的两个半寄存器。 寄存器中的位可以被加载到阵列的列中，并且因此被加载到寻址的单元行，或者一个整个寻址的单元行的数据可以经由列和传送门被加载到移位寄存器级。 对于写操作，来自外部的数据被串行地加载到移位寄存器中，在两个半寄存器之间逐位交替。 对于读操作，数据从寄存器中串行移出到外部，再次在半寄存器之间交替。 数据寄存器可以以两倍的时钟频率进行。 在数据被移入或移出串行寄存器的时间期间，单元阵列可被寻址以进行刷新。

公开(公告)号：US4110639A

公开(公告)日：1978-08-29

申请号：US748790

申请日：1976-12-09

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  H03K3/286 ,  G11C8/00 ,  H03K3/353

CPC classification number: G11C11/4093 ,  G11C11/4082 ,  G11C11/4091

Abstract: A high speed address buffer circuit for use in MOS/LSI semiconductor memories or the like. An unbalanced, dynamic cross-coupled pair of MOS driver transistors is used to sense an address input during a short time window, and internal address signals are generated from the state of the sense circuit. Sensing nodes are precharged and equalized prior to the time window, and the node which is to stay at the logic "1" level is held at a high level by boosting capacitors to which a delayed clock signal is applied. The state of the sense circuit is sampled at a time after the delayed clock and high level addresses are generated.

Abstract translation: 用于MOS / LSI半导体存储器等的高速地址缓冲电路。 使用不平衡的动态交叉耦合的MOS驱动晶体管对在短时间窗口期间感测地址输入，并且从感测电路的状态产生内部地址信号。 感测节点在时间窗口之前被预充电和均衡，并且要保持在逻辑“1”电平的节点通过升压施加延迟的时钟信号的电容器而保持在高电平。 在产生延迟的时钟和高电平地址之后的时间，对感测电路的状态进行采样。

公开(公告)号：US5451536A

公开(公告)日：1995-09-19

申请号：US252465

申请日：1994-06-01

Applicant: Donald J. Redwine

Inventor： Donald J. Redwine

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/402 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7831

Abstract: A power MOSFET device formed in a face of a semiconductor layer of a first conductivity type is provided. A first, second and third source region of a second conductivity type are formed in the face of the semiconductor layer within a moat and adjacent to its edges. A source conductor is insulatively disposed adjacent the face of the semiconductor layer and contacts the first, second and third source regions at a plurality of locations. A first and second drain region of a second conductivity type is also formed in the face of the semiconductor layer disposed spaced from and between the first and second source regions and the second and third source regions, respectively. A drain conductor is insulatively disposed adjacent the face of the semiconductor layer and contacts the first and second drain regions at a plurality of locations. A first and second field plate are insulatively disposed adjacent the face of the semiconductor layer and substantially adjacent and surrounding the first and second drain regions respectively. A first, second, third and fourth prongs forming gates of the device are insulatively disposed adjacent the face of the semiconductor layer and between the first field plate and the first and second source regions and between the second field plate and the second and third source regions. A portion of each of the gate prongs is disposed substantially above a portion of the first and second field plates. Conductive contacts connect the first and second field plates and the first and second drain regions.

Abstract translation: 提供了形成在第一导电类型的半导体层的表面上的功率MOSFET器件。 第二导电类型的第一，第二和第三源极区域形成在护城河内并且与其边缘相邻的半导体层的表面。 源极导体邻近半导体层的表面绝缘地设置并且在多个位置处接触第一，第二和第三源极区域。 第二导电类型的第一和第二漏极区域也分别形成在与第一和第二源极区域以及第二和第三源极区域之间隔开并位于其间的半导体层的表面上。 漏极导体邻近半导体层的表面绝缘地设置并且在多个位置处接触第一和第二漏极区域。 第一和第二场板被绝缘地布置成邻近半导体层的表面并且分别基本相邻并围绕第一和第二漏极区域。 形成器件的栅极的第一，第二，第三和第四尖端邻近半导体层的表面并且在第一场板与第一和第二源极区之间以及第二场板与第二和第三源极区之间 。 每个栅极插脚的一部分基本上设置在第一和第二场板的一部分上方。 导电触头连接第一和第二场板以及第一和第二漏极区域。

公开(公告)号：US5349225A

公开(公告)日：1994-09-20

申请号：US46571

申请日：1993-04-12

Applicant: Donald J. Redwine ,  Mousumi Bhat ,  Michael Smayling

Inventor： Donald J. Redwine ,  Mousumi Bhat ,  Michael Smayling

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L21/268

CPC classification number: H01L29/0847 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7836

Abstract: A transistor device 10 formed in a semiconductor layer 12 is disclosed herein. A first source/drain region 14 is formed in the semiconductor layer 12. A second source/drain region 16 is also formed in the semiconductor layer 12 and is spaced from the first source/drain region 14 by a channel region 18. The second source/drain region 16 includes (1) a lightly doped portion 16b adjacent the channel region 18 and abutting the top surface, (2) a main portion 16a abutting the top surface and spaced from the channel region 18 by the lightly doped portion 16b, and (3) a deep portion 16c formed within the layer 12 and spaced from the top surface by the lightly doped portion 16b and the main portion 16a. A gate electrode 20 is formed over at least a portion of the channel region 18 and insulated therefrom.

Abstract translation: 本文公开了形成在半导体层12中的晶体管器件10。 第一源极/漏极区域14形成在半导体层12中。第二源极/漏极区域16也形成在半导体层12中并且通过沟道区域18与第一源极/漏极区域14间隔开。第二源极 漏极区域16包括：（1）与沟道区域18相邻的轻微掺杂部分16b并邻接顶部表面;（2）与顶部表面邻接的主要部分16a，并且通过轻掺杂部分16b与沟道区域18隔开;以及 （3）形成在层12内并且由轻掺杂部分16b和主要部分16a与顶表面隔开的深部分16c。 栅电极20形成在通道区域18的至少一部分上并与其绝缘。