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21.发明申请公开(公告)号：US20070298578A1
公开(公告)日：2007-12-27
申请号：US11425550
申请日：2006-06-21
IPC分类号： H01L21/8228
CPC分类号： H01L29/7378 , H01L29/66242
摘要： An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair of neighboring first STI regions defines an active area in the substrate. The structure also includes a collector disposed in the in the active area of the semiconductor substrate, a base layer disposed atop a surface of the semiconductor substrate in the active area, and a raised extrinsic base disposed on the base layer. In accordance with the present, the raised extrinsic base has an opening to a portion of the base layer. An emitter is located in the opening and extending on a portion of the patterned raised extrinsic base; the emitter is spaced apart and isolated from the raised extrinsic base. Moreover, and in addition to the first STI region, a second shallow trench isolation (STI) region is present in the semiconductor substrate which extends inward from each pair of said first shallow trench isolation regions towards said collector. The second STI region has an inner sidewall surface that is sloped. In some embodiments, the base is completely monocrystalline.
摘要翻译： 提供了具有双浅沟槽隔离的改进的双极晶体管，用于减小基极与集电极电容Ccb和基极电阻Rb的寄生分量。 该结构包括具有设置在其中的至少一对相邻的第一浅沟槽隔离（STI）区域的半导体衬底。 该对相邻的第一STI区域限定衬底中的有源区域。 该结构还包括设置在半导体衬底的有源区域中的集电体，设置在有源区域中的半导体衬底的表面上的基极层和设置在基极层上的凸起的非本征基极。 根据本发明，凸起的外在基部具有对基底层的一部分的开口。 发射器位于开口中并且在图案化的凸起的外基极的一部分上延伸; 发射极间隔开并与凸起的外基极隔离。 而且，除了第一STI区之外，第二浅沟槽隔离（STI）区域存在于从每对所述第一浅沟槽隔离区向内朝向所述集电极延伸的半导体衬底中。 第二STI区域具有倾斜的内侧壁表面。 在一些实施方案中，碱是完全单晶的。
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22.发明授权Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration 有权双极晶体管具有凸起的外部自对准基极，使用BiCMOS集成的选择性外延生长公开(公告)号：US08525293B2
公开(公告)日：2013-09-03
申请号：US13472044
申请日：2012-05-15
IPC分类号： H01L29/73
CPC分类号： H01L29/7302 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66287
摘要： High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.
摘要翻译： 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。
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公开(公告)号：US20130005108A1
公开(公告)日：2013-01-03
申请号：US13610641
申请日：2012-09-11
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L21/8249 , H01L29/1004
摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
摘要翻译： 异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。 外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。 外基的表面可以被硅化。
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公开(公告)号：US08217497B2
公开(公告)日：2012-07-10
申请号：US11623922
申请日：2007-01-17
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L29/66181 , H01L29/945
摘要： The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode plate. Moreover, a semiconductor fin comprising a cathode is between the first vertical anode plate and the second vertical anode plate, wherein the semiconductor fin, the first vertical anode plate, and the second vertical anode plate are each positioned over the substrate and perpendicular to the upper surface of the substrate.
摘要翻译： 本发明的实施例提供了一种用于鳍式差分MOS变容二极管的结构，方法等。 更具体地，提供了一种差分变容二极管结构，包括具有上表面的衬底，第一垂直阳极板和与第一垂直阳极板电隔离的第二垂直阳极板。 此外，包括阴极的半导体鳍片在第一垂直阳极板和第二垂直阳极板之间，其中半导体鳍片，第一垂直阳极板和第二垂直阳极板分别位于衬底上并垂直于上部 基板的表面。
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25.发明申请BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION 有权使用选择性外延生长用于BICMOS整合的具有增强的自对准基底的双极晶体管公开(公告)号：US20110062548A1
公开(公告)日：2011-03-17
申请号：US12949108
申请日：2010-11-18
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L29/7302 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66287
摘要： High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.
摘要翻译： 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。
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26.发明申请公开(公告)号：US20080179703A1
公开(公告)日：2008-07-31
申请号：US11853973
申请日：2007-09-12
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L21/8249 , H01L27/0635 , H01L27/0814 , H01L29/161 , H01L29/47 , H01L29/66143
摘要： The structure for millimeter-wave frequency applications, includes a Schottky barrier diode (SBD) with a cutoff frequency (FC) above 1.0 THz formed on a SiGe BiCMOS wafer. A method is also contemplated for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
摘要翻译： 毫米波频率应用的结构包括在SiGe BiCMOS晶片上形成的截止频率（F SUB）高于1.0THz的肖特基势垒二极管（SBD）。 还考虑了在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（F SUB）的结构。 在实施例中，提供约1.0THz以上的截止频率（F SUB）的结构可以包括具有提供上述截止频率（F SUB C）的阳极区域的阳极 约1.0THz，具有提供高于约1.0THz的截止频率（F SUB）的厚度的n外延层，以能量和剂量提供截止频率（F）的p型防护 在约1.0THz以上的p型防护装置，具有提供高于约1.0THz的截止频率（F SUB C）的尺寸，以及具有n 型掺杂剂，其在约1.0THz以上提供截止频率（F C C）。
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公开(公告)号：US20080169495A1
公开(公告)日：2008-07-17
申请号：US11623922
申请日：2007-01-17
IPC分类号： H01L29/93 , H01L21/329
CPC分类号： H01L29/93 , H01L29/66181 , H01L29/945
摘要： The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode plate. Moreover, a semiconductor fin comprising a cathode is between the first vertical anode plate and the second vertical anode plate, wherein the semiconductor fin, the first vertical anode plate, and the second vertical anode plate are each positioned over the substrate and perpendicular to the upper surface of the substrate.
摘要翻译： 本发明的实施例提供了一种用于鳍式差分MOS变容二极管的结构，方法等。 更具体地，提供了一种差分变容二极管结构，包括具有上表面的衬底，第一垂直阳极板和与第一垂直阳极板电隔离的第二垂直阳极板。 此外，包括阴极的半导体鳍片在第一垂直阳极板和第二垂直阳极板之间，其中半导体鳍片，第一垂直阳极板和第二垂直阳极板分别位于衬底上并垂直于上部 基板的表面。
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28.发明授权公开(公告)号：US08592293B2
公开(公告)日：2013-11-26
申请号：US13028673
申请日：2011-02-16
IPC分类号： H01L21/28
CPC分类号： H01L29/872 , H01L21/8249 , H01L27/0635 , H01L27/0814 , H01L29/161 , H01L29/47 , H01L29/66143
摘要： A method for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
摘要翻译： 一种在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（Fc）的结构。 在实施例中，提供高于约1.0THz的截止频率（Fc）的结构可以包括具有提供高于约1.0THz的截止频率（FC）的阳极区域的阳极，具有提供截止频率 频率（FC）高于约1.0THz，在提供高于约1.0THz的截止频率（FC）的能量和剂量下的p型防护，所述p型护罩具有提供高于约截止频率（FC）的尺寸 1.0 THz，以及具有n型掺杂剂的良好裁缝，其提供高于约1.0THz的截止频率（FC）。
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29.发明申请BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION 有权使用选择性外延生长用于BICMOS整合的具有增强的自对准基底的双极晶体管公开(公告)号：US20120319233A1
公开(公告)日：2012-12-20
申请号：US13472044
申请日：2012-05-15
IPC分类号： H01L29/73
CPC分类号： H01L29/7302 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66287
摘要： High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.
摘要翻译： 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。
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30.发明授权公开(公告)号：US07936041B2
公开(公告)日：2011-05-03
申请号：US11853973
申请日：2007-09-12
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L21/8249 , H01L27/0635 , H01L27/0814 , H01L29/161 , H01L29/47 , H01L29/66143
摘要： The structure for millimeter-wave frequency applications, includes a Schottky barrier diode (SBD) with a cutoff frequency (FC) above 1.0 THz formed on a SiGe BiCMOS wafer. A method is also contemplated for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
摘要翻译： 毫米波频率应用的结构包括在SiGe BiCMOS晶片上形成的截止频率（FC）大于1.0THz的肖特基势垒二极管（SBD）。 还考虑了在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（Fc）的结构。 在实施例中，提供高于约1.0THz的截止频率（Fc）的结构可以包括具有提供高于约1.0THz的截止频率（FC）的阳极区域的阳极，具有提供截止频率 频率（FC）高于约1.0THz，在提供高于约1.0THz的截止频率（FC）的能量和剂量下的p型防护，所述p型护罩具有提供高于约截止频率（FC）的尺寸 1.0 THz，以及具有n型掺杂剂的良好裁缝，其提供高于约1.0THz的截止频率（FC）。
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