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公开(公告)号：US08912574B2
公开(公告)日：2014-12-16
申请号：US12967771
申请日：2010-12-14
申请人： Mattias E. Dahlstrom , Dinh Dang , Qizhi Liu , Ramana M. Malladi
发明人： Mattias E. Dahlstrom , Dinh Dang , Qizhi Liu , Ramana M. Malladi
IPC分类号： H01L21/763 , H01L23/367 , H01L21/762 , H01L29/08 , H01L29/66 , H01L29/737
CPC分类号： H01L29/66242 , H01L21/30604 , H01L21/308 , H01L21/76224 , H01L21/763 , H01L23/367 , H01L23/3677 , H01L23/373 , H01L29/0821 , H01L29/7371 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.
摘要翻译： 制造半导体结构的方法包括通过浅沟槽隔离（STI）结构形成沟槽并且形成衬底，以及在沟槽的侧壁上形成包括电绝缘体材料的衬垫。 该方法还包括在沟槽和衬垫上形成包括高导热性材料的芯，并在沟槽和芯上形成帽。
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2.发明申请TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE 有权具有侧向定义的内部基极到极端基底连接区域的晶体管结构及形成结构的方法公开(公告)号：US20110309471A1
公开(公告)日：2011-12-22
申请号：US12817249
申请日：2010-06-17
申请人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/732 , H01L29/66242 , H01L29/66287 , H01L29/7378
摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.
摘要翻译： 公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。 结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极 电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度 发射极层）进行选择性调整，以优化晶体管性能。
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3.发明授权Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure 有权具有侧壁限定的内在基极到外部基极连接区域的晶体管结构和形成该结构的方法公开(公告)号：US08405186B2
公开(公告)日：2013-03-26
申请号：US12817249
申请日：2010-06-17
申请人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
IPC分类号： H01L21/70
CPC分类号： H01L29/732 , H01L29/66242 , H01L29/66287 , H01L29/7378
摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.
摘要翻译： 公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。 结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极 电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度 发射极层）进行选择性调整，以优化晶体管性能。
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4.发明授权Bipolar transistor with dual shallow trench isolation and low base resistance 有权具有双浅沟槽隔离和低基极电阻的双极晶体管公开(公告)号：US07888745B2
公开(公告)日：2011-02-15
申请号：US11425550
申请日：2006-06-21
IPC分类号： H01L29/72
CPC分类号： H01L29/7378 , H01L29/66242
摘要： An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair of neighboring first STI regions defines an active area in the substrate. The structure also includes a collector disposed in the in the active area of the semiconductor substrate, a base layer disposed atop a surface of the semiconductor substrate in the active area, and a raised extrinsic base disposed on the base layer. In accordance with the present, the raised extrinsic base has an opening to a portion of the base layer. An emitter is located in the opening and extending on a portion of the patterned raised extrinsic base; the emitter is spaced apart and isolated from the raised extrinsic base. Moreover, and in addition to the first STI region, a second shallow trench isolation (STI) region is present in the semiconductor substrate which extends inward from each pair of said first shallow trench isolation regions towards said collector. The second STI region has an inner sidewall surface that is sloped. In some embodiments, the base is completely monocrystalline.
摘要翻译： 提供了具有双浅沟槽隔离的改进的双极晶体管，用于减小基极与集电极电容Ccb和基极电阻Rb的寄生分量。 该结构包括具有设置在其中的至少一对相邻的第一浅沟槽隔离（STI）区域的半导体衬底。 该对相邻的第一STI区域限定衬底中的有源区域。 该结构还包括设置在半导体衬底的有源区域中的集电体，设置在有源区域中的半导体衬底的表面上的基极层和设置在基极层上的凸起的非本征基极。 根据本发明，凸起的外在基部具有对基底层的一部分的开口。 发射器位于开口中并在图案化的凸起的外基极的一部分上延伸; 发射极间隔开并与凸起的外基极隔离。 而且，除了第一STI区之外，第二浅沟槽隔离（STI）区域存在于从每对所述第一浅沟槽隔离区向内朝向所述集电极延伸的半导体衬底中。 第二STI区域具有倾斜的内侧壁表面。 在一些实施方案中，碱是完全单晶的。
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公开(公告)号：US20120146098A1
公开(公告)日：2012-06-14
申请号：US12967771
申请日：2010-12-14
申请人： Mattias E. DAHLSTROM , Dinh DANG , Qizhi LIU , Ramana M. MALLADI
发明人： Mattias E. DAHLSTROM , Dinh DANG , Qizhi LIU , Ramana M. MALLADI
IPC分类号： H01L29/70 , H01L21/328 , H01L21/762
CPC分类号： H01L29/66242 , H01L21/30604 , H01L21/308 , H01L21/76224 , H01L21/763 , H01L23/367 , H01L23/3677 , H01L23/373 , H01L29/0821 , H01L29/7371 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.
摘要翻译： 制造半导体结构的方法包括通过浅沟槽隔离（STI）结构形成沟槽并且形成衬底，以及在沟槽的侧壁上形成包括电绝缘体材料的衬垫。 该方法还包括在沟槽和衬垫上形成包括高导热性材料的芯，并在沟槽和芯上形成帽。
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6.发明申请公开(公告)号：US20070298578A1
公开(公告)日：2007-12-27
申请号：US11425550
申请日：2006-06-21
IPC分类号： H01L21/8228
CPC分类号： H01L29/7378 , H01L29/66242
摘要： An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair of neighboring first STI regions defines an active area in the substrate. The structure also includes a collector disposed in the in the active area of the semiconductor substrate, a base layer disposed atop a surface of the semiconductor substrate in the active area, and a raised extrinsic base disposed on the base layer. In accordance with the present, the raised extrinsic base has an opening to a portion of the base layer. An emitter is located in the opening and extending on a portion of the patterned raised extrinsic base; the emitter is spaced apart and isolated from the raised extrinsic base. Moreover, and in addition to the first STI region, a second shallow trench isolation (STI) region is present in the semiconductor substrate which extends inward from each pair of said first shallow trench isolation regions towards said collector. The second STI region has an inner sidewall surface that is sloped. In some embodiments, the base is completely monocrystalline.
摘要翻译： 提供了具有双浅沟槽隔离的改进的双极晶体管，用于减小基极与集电极电容Ccb和基极电阻Rb的寄生分量。 该结构包括具有设置在其中的至少一对相邻的第一浅沟槽隔离（STI）区域的半导体衬底。 该对相邻的第一STI区域限定衬底中的有源区域。 该结构还包括设置在半导体衬底的有源区域中的集电体，设置在有源区域中的半导体衬底的表面上的基极层和设置在基极层上的凸起的非本征基极。 根据本发明，凸起的外在基部具有对基底层的一部分的开口。 发射器位于开口中并且在图案化的凸起的外基极的一部分上延伸; 发射极间隔开并与凸起的外基极隔离。 而且，除了第一STI区之外，第二浅沟槽隔离（STI）区域存在于从每对所述第一浅沟槽隔离区向内朝向所述集电极延伸的半导体衬底中。 第二STI区域具有倾斜的内侧壁表面。 在一些实施方案中，碱是完全单晶的。
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7.发明授权Bipolar transistor structure and method including emitter-base interface impurity 有权双极晶体管结构和方法包括发射极 - 基极界面杂质公开(公告)号：US08482101B2
公开(公告)日：2013-07-09
申请号：US12488899
申请日：2009-06-22
IPC分类号： H01L29/66
CPC分类号： H01L29/732 , H01L29/0821 , H01L29/0826 , H01L29/167 , H01L29/207 , H01L29/227 , H01L29/34 , H01L29/66272
摘要： A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.
摘要翻译： 双极晶体管结构和制造双极晶体管结构的方法包括：（1）至少部分地位于半导体衬底内的集电极结构; （2）与收集器结构接触的基部结构; 和（3）与基底结构接触的发射体结构。 发射极结构和基极结构的界面包括氧杂质和选自氟杂质和碳杂质的至少一种杂质，以增强双极晶体管结构内的双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或者替代地进行无水氨和氟化氢处理的热处理而引入到界面中，其中基体材料由基底结构组成。
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8.发明申请BIPOLAR TRANSISTOR STRUCTURE AND METHOD INCLUDING EMITTER-BASE INTERFACE IMPURITY 有权双极晶体管结构和方法，其中包括发射极基底界面强度公开(公告)号：US20100320571A1
公开(公告)日：2010-12-23
申请号：US12488899
申请日：2009-06-22
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/732 , H01L29/0821 , H01L29/0826 , H01L29/167 , H01L29/207 , H01L29/227 , H01L29/34 , H01L29/66272
摘要： A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.
摘要翻译： 双极晶体管结构和制造双极晶体管结构的方法包括：（1）至少部分地位于半导体衬底内的集电极结构; （2）与收集器结构接触的基部结构; 和（3）与基底结构接触的发射体结构。 发射极结构和基极结构的界面包括氧杂质和选自氟杂质和碳杂质的至少一种杂质，以增强双极晶体管结构内的双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或者替代地进行无水氨和氟化氢处理的热处理而引入到界面中，其中基体材料由基底结构组成。
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