公开(公告)号：US07923782B2

公开(公告)日：2011-04-12

申请号：US10708378

申请日：2004-02-27

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L27/01 ,  H01L27/12

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US07388257B2

公开(公告)日：2008-06-17

申请号：US10711200

申请日：2004-09-01

申请人： Bruce B. Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.

摘要翻译： 多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。 高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。 在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。 保护层可以在蚀刻过程中保护高k电介质层。

公开(公告)号：US07785943B2

公开(公告)日：2010-08-31

申请号：US11928787

申请日：2007-10-30

申请人： Bruce B. Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Method for providing a transistor that includes the steps of providing a silicon on insulator layer, providing a silicon oxide insulation layer, providing a dielectric layer, removing at least a portion of the silicon oxide insulation layer and the dielectric layer to form a gate stack, and forming a gate electrode. The gate electrode covers a portion of the gate stack.

摘要翻译： 一种用于提供晶体管的方法，包括以下步骤：提供绝缘体上硅层，提供氧化硅绝缘层，提供电介质层，去除氧化硅绝缘层和电介质层的至少一部分以形成栅叠层; 并形成栅电极。 栅电极覆盖栅叠层的一部分。

公开(公告)号：US20080142852A1

公开(公告)日：2008-06-19

申请号：US12032913

申请日：2008-02-18

申请人： Bruce B. Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

IPC分类号： H01L27/092

CPC分类号： H01L29/045 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7842

摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.

摘要翻译： 公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。 该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。 半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个 其他。

公开(公告)号：US20080246090A1

公开(公告)日：2008-10-09

申请号：US12119765

申请日：2008-05-13

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

IPC分类号： H01L27/12

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

摘要翻译： 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

公开(公告)号：US07271446B2

公开(公告)日：2007-09-18

申请号：US10916814

申请日：2004-08-12

申请人： Omer H. Dokumaci ,  Bruce B. Doris

发明人： Omer H. Dokumaci ,  Bruce B. Doris

IPC分类号： H01L27/01

CPC分类号： H01L29/66772 ,  H01L21/2255 ,  H01L29/6656 ,  H01L29/78621

摘要： The inventive method for forming thin channel MOSFETS comprises: providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material; forming a conformal oxide film atop the structure; implanting the conformal oxide film; forming a set of spacers atop the conformal oxide film, said set of sidewall spacers are adjacent to the gate region; removing portions of the oxide film, not protected by the set of spacers to expose a region of the semiconducting material; forming raised source/drain regions on the exposed region of the semiconducting material; implanting the raised source/drain regions with a second dopant impurity to form a second dopant impurity region; and annealing a final structure to provide a thin channel MOSFET.

摘要翻译： 用于形成薄沟道MOSFET的本发明的方法包括：提供至少包括在绝缘层顶部具有半导体材料层的衬底和形成在半导体材料层顶上的栅极区域的结构的结构; 在结构顶部形成保形氧化膜; 植入保形氧化膜; 在所述共形氧化物膜的上方形成一组间隔物，所述一组侧壁间隔物邻近所述栅极区; 去除未被所述一组间隔物保护的氧化膜的部分以暴露所述半导体材料的区域; 在所述半导体材料的暴露区域上形成凸起的源极/漏极区域; 用第二掺杂杂质注入凸起的源/漏区以形成第二掺杂杂质区; 并退火最终结构以提供薄沟道MOSFET。

公开(公告)号：US06645867B2

公开(公告)日：2003-11-11

申请号：US09864974

申请日：2001-05-24

申请人： Omer H. Dokumaci ,  Bruce B. Doris

发明人： Omer H. Dokumaci ,  Bruce B. Doris

IPC分类号： H01L21301

CPC分类号： H01L21/31144 ,  H01L21/3185 ,  H01L21/76224 ,  H01L21/76283

摘要： Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.

公开(公告)号：US06780694B2

公开(公告)日：2004-08-24

申请号：US10338930

申请日：2003-01-08

申请人： Bruce B. Doris ,  Omer H. Dokumaci ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Bruce B. Doris ,  Omer H. Dokumaci ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L21338

CPC分类号： H01L21/28114 ,  H01L21/26586 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665

摘要： A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate. Form silicide layers on top of the T-shaped gate electrode and above the source/drain regions.

摘要翻译： 制造半导体晶体管器件的方法包括以下步骤。 提供其上具有栅极介电层的半导体衬底和形成在栅极电介质层上的下部栅极电极结构，而下部栅电极结构具有较低的栅极顶部。 在栅极电介质层上形成平坦化层，离开下部栅电极结构的栅极顶部。 在下栅极电极结构上形成上栅极结构，形成具有上栅极表面的暴露下表面和暴露的栅电极垂直侧壁的T形栅电极。 取出平坦化层。 衬底中形成源/漏极扩展，防止短沟道效应。 形成邻近上部栅极的暴露的下表面和T形栅电极的暴露的垂直侧壁的侧壁间隔物。 在衬底中形成源/漏区。 在T形栅电极的顶部和源极/漏极区之上形成硅化物层。

公开(公告)号：US06562713B1

公开(公告)日：2003-05-13

申请号：US10078779

申请日：2002-02-19

申请人： Michael P. Belyansky ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Hussein I. Hanafi

发明人： Michael P. Belyansky ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Hussein I. Hanafi

IPC分类号： H01L214763

CPC分类号： H01L29/66545 ,  H01L21/823456

摘要： Disclosed is a method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma layer of a silicon compound, selected from the group silicon oxide and silicon nitride, in a manner effective in leaving an upper surface of said gate exposed. Also disclosed is a method of processing short gates while protecting long gates on a semiconductor surface, the method comprising depositing a planarizing layer of a silicon compound, selected from the group silicon nitride and silicon oxide, up to substantially the same height as said gates, and processing said semiconductor surface.

摘要翻译： 公开了一种保护半导体区域同时暴露栅极以在半导体表面上进行处理的方法，该方法包括以有效离开的方式沉积选自硅氧化物和氮化硅的硅化合物的平面化高密度等离子体层 所述门的上表面暴露。 还公开了一种处理短栅极同时保护半导体表面上的长栅极的方法，该方法包括沉积选自氮化硅和氧化硅的硅化合物的平坦化层，其高达与所述栅极基本相同的高度， 并处理所述半导体表面。

公开(公告)号：US07453123B2

公开(公告)日：2008-11-18

申请号：US11676030

申请日：2007-02-16

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

IPC分类号： H01L27/01

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

摘要翻译： 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 在器件层上方的前栅极热氧化物：位于前栅极热氧化物上方并与背栅电极垂直对准的前栅极电极层; 以及设置在所述背栅极热氧化物层上方的与所述第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。