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公开(公告)号：US06878582B2
公开(公告)日：2005-04-12
申请号：US10876873
申请日：2004-06-25
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.
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公开(公告)号：US06780694B2
公开(公告)日：2004-08-24
申请号：US10338930
申请日：2003-01-08
IPC分类号： H01L21338
CPC分类号： H01L21/28114 , H01L21/26586 , H01L21/82385 , H01L21/823864 , H01L29/42376 , H01L29/665
摘要： A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate. Form silicide layers on top of the T-shaped gate electrode and above the source/drain regions.
摘要翻译： 制造半导体晶体管器件的方法包括以下步骤。 提供其上具有栅极介电层的半导体衬底和形成在栅极电介质层上的下部栅极电极结构，而下部栅电极结构具有较低的栅极顶部。 在栅极电介质层上形成平坦化层，离开下部栅电极结构的栅极顶部。 在下栅极电极结构上形成上栅极结构，形成具有上栅极表面的暴露下表面和暴露的栅电极垂直侧壁的T形栅电极。 取出平坦化层。 衬底中形成源/漏极扩展，防止短沟道效应。 形成邻近上部栅极的暴露的下表面和T形栅电极的暴露的垂直侧壁的侧壁间隔物。 在衬底中形成源/漏区。 在T形栅电极的顶部和源极/漏极区之上形成硅化物层。
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公开(公告)号：US06841826B2
公开(公告)日：2005-01-11
申请号：US10345472
申请日：2003-01-15
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.
摘要翻译： 低GIDL电流MOSFET器件结构及其制造方法，其提供低GIDL电流。 MOSFET器件结构包含中心栅极导体，其边缘可能与源极/漏极扩散稍微重叠，以及通过薄的绝缘和扩散阻挡层与中心栅极导体分离的左侧和右侧翼栅极导体。
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公开(公告)号：US06806534B2
公开(公告)日：2004-10-19
申请号：US10342423
申请日：2003-01-14
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/26586 , H01L21/28114 , H01L29/665 , H01L29/66553
摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.
摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。 当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。 高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。 由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。
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公开(公告)号：US07374987B2
公开(公告)日：2008-05-20
申请号：US10935136
申请日：2004-09-07
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/42316 , H01L29/7842 , H01L29/7843 , H01L29/808
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.
摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。 另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。
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公开(公告)号：US06974981B2
公开(公告)日：2005-12-13
申请号：US10318600
申请日：2002-12-12
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L29/80 , H01L31/109 , H01L31/112 , H01L29/774
CPC分类号： H01L29/7846 , H01L21/76232 , H01L21/823807 , H01L21/823878 , H01L29/785
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.
摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择适当的STI填充材料将张力和/或压缩施加在基底上。 STI区域形成在衬底层中并且在相邻衬底区域上施加力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，实现了IC性能的提高。
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公开(公告)号：US06825529B2
公开(公告)日：2004-11-30
申请号：US10318602
申请日：2002-12-12
IPC分类号： H01L2976
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/42316 , H01L29/7842 , H01L29/7843 , H01L29/808
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.
摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。 另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。
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8.发明授权Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效在单元中并联连接沟槽电容器的多端口存储器制造方法公开(公告)号：US07785959B2
公开(公告)日：2010-08-31
申请号：US12316748
申请日：2008-12-16
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译： 提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。 形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。 第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。 以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。
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公开(公告)号：US07138685B2
公开(公告)日：2006-11-21
申请号：US10318495
申请日：2002-12-11
IPC分类号： H01L21/00
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
摘要翻译： 形成SRAM单元装置的方法包括以下步骤。 形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为平坦绝缘体上形成平行岛的硅层。 通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到 到共同的身体层。 形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。 然后，连接FET晶体管以形成SRAM单元。
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10.发明授权Memory cell with vertical transistor and trench capacitor with reduced burried strap 有权具有垂直晶体管和沟槽电容器的存储单元，具有减少的挂带公开(公告)号：US06759702B2
公开(公告)日：2004-07-06
申请号：US10261559
申请日：2002-09-30
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/66181 , H01L29/945
摘要： A memory cell structure including a semiconductor substrate, a deep (e.g., longitudinal) trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom, a buried strap along a sidewall of the deep trench, a storage capacitor at the bottom of the deep trench, a vertical transistor extending down the sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench, a collar oxide extending down another sidewall of the deep trench opposite the capacitor, shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends, a gate conductor extending within the deep trench, a wordline extending over the deep trench and connected to the gate conductor, and a bitline extending above the surface plane of the substrate having a contact to the diffusion between the shallow trench isolation regions. The deep trench has a perimeter in a direction normal to its depth, and the buried strap extends a distance along the perimeter, the distance being only within a range of 5% to 20% of the entire linear distance along the perimeter, and being less than one lithographic feature size. Preferably, the strap in a direction along the perimeter is curved and is disposed along only one corner of the perimeter. The structure is particularly useful for a sub-8F2 cell.
摘要翻译： 一种存储单元结构，包括半导体衬底，半导体衬底中的深（例如，纵向）沟槽，深沟槽具有多个侧壁和底部，沿着深沟槽的侧壁的掩埋带，存储电容器 深沟槽的底部，垂直晶体管，沿着存储电容器上方的深沟槽的侧壁向下延伸，晶体管具有在衬底的与深沟槽相邻的平面中延伸的扩散，从深沟槽的另一个侧壁延伸的环状氧化物 与电容器相对的浅沟槽隔离区域沿垂直于垂直晶体管延伸的侧壁横向的衬底表面延伸，在深沟槽内延伸的栅极导体，延伸在深沟槽上并与栅极导体连接的字线 以及在衬底的表面平面上方延伸的位线，该位线与浅沟槽iso之间的扩散接触 国际地区。 深沟槽在垂直于其深度的方向上具有周长，并且掩埋带沿着周边延伸一段距离，该距离仅在沿着周边的整个线性距离的5％至20％的范围内，并且更小 比一个光刻特征尺寸。 优选地，沿着周边的方向上的带子是弯曲的并且沿着周边的一个角部设置。 该结构对于亚8F 2细胞特别有用。
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