公开(公告)号：US08198703B2

公开(公告)日：2012-06-12

申请号：US12689120

申请日：2010-01-18

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

IPC分类号： H01L29/06

CPC分类号： H01L29/0646 ,  H01L29/0692 ,  H01L29/8611 ,  H01L29/866

摘要： A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.

摘要翻译： 在其上具有半导体材料的半导体衬底上制造齐纳二极管。 齐纳二极管包括形成在半导体材料中的具有第一导电类型的第一阱区。 齐纳二极管还包括形成在第一阱区（第二导电类型与第一导电类型相反）的第二导电类型的第一区。 齐纳二极管还包括具有第一导电类型的第二区域，其中第二区域形成在第一阱区域中并且覆盖第一区域。 在第一区域中形成电极，并且电极电连接到第二区域。

公开(公告)号：US07972913B2

公开(公告)日：2011-07-05

申请号：US12474038

申请日：2009-05-28

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

IPC分类号： H01L21/338

CPC分类号： H01L29/808 ,  H01L29/0619 ,  H01L29/66143 ,  H01L29/66901 ,  H01L29/806 ,  H01L29/872

摘要： Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.

摘要翻译： 通过以串联位于包括肖特基接触和第二端子的第一端子之间的第一导电类型的电流路径构建JFET来提供具有减小的漏电流和改善的击穿电压的改进的肖特基二极管。 电流通路是（i）在肖特基接触的基本上横向外侧的第二相对导电类型的多个基本上平行的手指区域之间，以及（ii）部分地位于第二导电类型的掩埋区域之下， 路径，哪些区域电耦合到第一端子和肖特基接触，哪个部分电耦合到第二端子。 当对第一端子和肖特基接触器施加反向偏压时，电流路径在垂直或水平方向或两者上基本上被夹断，从而减小漏电流并提高器件的击穿电压。

公开(公告)号：US07915704B2

公开(公告)日：2011-03-29

申请号：US12359845

申请日：2009-01-26

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/66143

摘要： Improved Schottky diodes (20) with reduced leakage current and improved breakdown voltage are provided by building a JFET (56) into the diode, serially located in the anode-cathode current path (32). The gates of the JFET (56) formed by doped regions (38, 40) placed above and below the diode's current path (32) are coupled to the anode (312) of the diode (20), and the current path (32) passes through the channel region (46) of the JFET (56). Operation is automatic so that as the reverse voltage increases, the JFET (56) channel region (46) pinches off, thereby limiting the leakage current and clamping the voltage across the Schottky junction (50) at a level below the Schottky junction (50) breakdown. Increased reverse voltage can be safely applied until the device eventually breaks down elsewhere. The impact on device area and area efficiency is minimal and the device can be built using a standard fabrication process so that it can be easily integrated into complex ICs.

摘要翻译： 通过在串联地位于阳极 - 阴极电流路径（32）中的二极管中构建JFET（56）来提供具有减小的漏电流和改善的击穿电压的改进的肖特基二极管（20）。 由位于二极管电流路径（32）上方和下方的掺杂区域（38,40）形成的JFET（56）的栅极耦合到二极管（20）的阳极（312），并且电流路径（32） 通过JFET（56）的沟道区（46）。 操作是自动的，使得当反向电压增加时，JFET（56）沟道区域（46）夹紧，由此限制漏电流并将肖特基结（50）上的电压钳位在低于肖特基结（50）的水平处， 分解。 可以安全地应用增加的反向电压，直到器件最终在其他地方崩溃。 对器件面积和面积效率的影响最小，可以使用标准制造工艺构建器件，从而可以轻松集成到复杂IC中。

公开(公告)号：US20100301400A1

公开(公告)日：2010-12-02

申请号：US12474038

申请日：2009-05-28

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/808 ,  H01L29/0619 ,  H01L29/66143 ,  H01L29/66901 ,  H01L29/806 ,  H01L29/872

摘要： Improved Schottky diodes (20, 20′) with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path (50, 50′) of a first conductivity type serially located between a first terminal (80, 80′, 32, 32′) comprising a Schottky contact (33, 33′) and a second (82, 82′, 212, 212′) terminal. The current path (50, 50′) lies (i) between multiple substantially parallel finger regions (36, 36′) of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact (33, 33′), and (ii) partly above a buried region (44, 44′) of the second conductivity type that underlies a portion (46, 46′) of the current path (50, 50′), which regions (36, 36′; 44, 44′) are electrically coupled to the first terminal (80, 80′, 32, 32′) and the Schottky contact (33, 33′) and which portion (46, 46′) is electrically coupled to the second terminal (82, 82′, 212, 212′). When reverse bias is applied to the first terminal (80, 80′, 32, 32′) and Schottky contact (33, 33′), the current path (50, 50′) is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device (20, 20′).

摘要翻译： 通过构建JFET的电流路径（50,50'）提供具有减小的漏电流和改善的击穿电压的改进的肖特基二极管（20,20'），该电流路径（50,50'）串联地位于第一端子（80,80'， 32,32'），包括肖特基接触（33,33'）和第二（82,82'，212,212'）端子。 电流路径（50,50'）位于（i）在肖特基接触（33,33'）基本上横向外侧的第二相对导电类型的多个基本平行的手指区域（36,36'）之间，和（ii ）部分地位于位于电流路径（50,50'）的一部分（46,46'）下方的第二导电类型的埋入区（44,44'），该区域（36,36'; 44,44'） ）电耦合到第一端子（80,80'，32,32'）和肖特基接触（33,33'），并且哪个部分（46,46'）电耦合到第二端子（82,82'）， ，212,212'）。 当对第一端子（80,80'，32,32'）和肖特基接触（33,33'）施加反向偏压时，电流路径（50,50'）在垂直或水平方向上基本上被夹紧或者两者都是 从而减小漏电流并提高器件（20,20'）的击穿电压。

公开(公告)号：US09893164B2

公开(公告)日：2018-02-13

申请号：US14844608

申请日：2015-09-03

申请人： Xin Lin ,  Daniel J Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J Blomberg ,  Jiang-Kai Zuo

IPC分类号： H02H9/04 ,  H01L21/331 ,  H01L29/73 ,  H01L27/02 ,  H01L29/66 ,  H01L29/735 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/6625 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/735

摘要： A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.

公开(公告)号：US09490322B2

公开(公告)日：2016-11-08

申请号：US13748076

申请日：2013-01-23

申请人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/94 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/66681 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.

摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域以及沿着第一横向尺寸彼此间隔开的半导体衬底中的漂移区域，并且在施加偏置电压之前电荷载体在操作期间漂移 源极和漏极区域。 漂移区域沿着漂移区域和漏极区域之间的界面在第二横向维度上具有缺口掺杂剂分布。

公开(公告)号：US09466687B2

公开(公告)日：2016-10-11

申请号：US14157317

申请日：2014-01-16

申请人： Xin Lin ,  Daniel J. Blomberg ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L21/331 ,  H01L29/66 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/735

CPC分类号： H01L29/6625 ,  H01L21/82285 ,  H01L27/0826 ,  H01L29/735

摘要： Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.

摘要翻译： 通过提供与晶体管表面上的发射极相同的导电类型的另外的掺杂区域，可以减少或消除具有延伸到发射极和基极接触之间的晶体管表面的基极的一部分的双极晶体管中的不稳定性和漂移 在发射极和基极之间。 另外的区域期望比表面上的基极区域重掺杂，并且比相邻的发射极更重掺杂。 在另一个实施例中，与发射器相同的导电类型的仍然还是另外的区域被提供在另外的区域和发射极之间或者在发射极内侧。 仍然还是进一步的区域期望比其他区域更重掺杂。 这样的另外的区域屏蔽近表面碱基区域可能存在于覆盖晶体管表面的电介质层或界面中的俘获电荷。

公开(公告)号：US20150325565A1

公开(公告)日：2015-11-12

申请号：US14272027

申请日：2014-05-07

申请人： Hongning Yang ,  Xin Lin ,  Pete Rodriguez ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Xin Lin ,  Pete Rodriguez ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L27/02 ,  H01L29/08 ,  H01L21/265 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L27/0248 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0266 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor.

摘要翻译： 一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构， 另一个。 第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。 第一多个晶体管结构的每个晶体管结构包括非均匀沟道，使得第一构成晶体管具有比第二构成晶体管更高的阈值电压电平。

公开(公告)号：US09107942B2

公开(公告)日：2015-08-18

申请号：US13126875

申请日：2009-11-02

申请人： Jia Guo ,  Xin Lin ,  Steve Georas ,  Patricia Sime

发明人： Jia Guo ,  Xin Lin ,  Steve Georas ,  Patricia Sime

IPC分类号： A61K45/00 ,  A61K31/7088 ,  A61K39/395 ,  C12Q1/68

CPC分类号： G01N33/6875 ,  A61K31/7088 ,  A61K31/713 ,  A61K38/44 ,  A61K39/395 ,  A61K39/39533 ,  A61K39/39583 ,  A61K45/00 ,  C12Q1/6883 ,  C12Q2600/106 ,  C12Q2600/112 ,  C12Q2600/136 ,  C12Q2600/154 ,  C12Q2600/158 ,  C12Y114/11027 ,  G01N2800/10 ,  G01N2800/52

摘要： The present invention is directed to methods of diagnosing and treating a fibrotic condition in a mammalian subject. These methods involve measuring the levels of trimethylation at lysine residue 27 of histone-3 and/or measuring the expression levels of EZH2 or YY-1. Agents useful for treating fibrosis or a fibrotic condition are also disclosed.

摘要翻译： 本发明涉及在哺乳动物受试者中诊断和治疗纤维化病症的方法。 这些方法包括测量组蛋白-3的赖氨酸残基27处的三甲基化水平和/或测量EZH2或YY-1的表达水平。 还公开了可用于治疗纤维化或纤维化病症的药剂。

公开(公告)号：US09105657B2

公开(公告)日：2015-08-11

申请号：US14071344

申请日：2013-11-04

申请人： Hongning Yang ,  Xin Lin ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Xin Lin ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/66681 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7801 ,  H01L29/7816

摘要： Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space adjacent the drain, is avoided by providing a lightly doped region of a first conductivity type (CT) separating the first CT drift space from an opposite CT WELL region in which the first CT source is located, and a further region of the opposite CT (e.g., formed by an angled implant) extending through part of the WELL region under an edge of the gate located near a boundary of the WELL region into the lightly doped region, and a shallow still further region of the first CT Ohmically coupled to the source and ending near the gate edge whereby the effective channel length in the further region is reduced to near zero. Substantial improvement in BVDSS and/or Rdson can be obtained without degrading the other or significant adverse affect on other device properties.

摘要翻译： 通过提供将第一CT漂移空间与相对的CT WELL区域分开的第一导电类型（CT）的轻掺杂区域来避免采用邻近漏极的漂移空间的LDMOS器件中的BVDSS和Rdson之间的不利权衡，其中第一CT 源和位于WELL区附近的位于边缘边缘的WELL区域的一部分延伸穿入部分WELL区域的另一区域（例如由成角度的植入物形成）进入轻掺杂区域，以及 第一CT的较浅的另一区域欧姆耦合到源极并且在栅极边缘附近结束，由此在另一区域中的有效沟道长度减小到接近零。 可以获得BVDSS和/或Rdson的显着改善，而不会降低对其他设备性能的其他影响或显着的不利影响。