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公开(公告)号：US20200382223A1
公开(公告)日：2020-12-03
申请号：US16881657
申请日：2020-05-22
Inventor： Hyuk KIM , Hyung-IL PARK , Tae Wook KANG , Sung Eun KIM , Mi Jeong PARK , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE , In Gi LIM
IPC: H04B13/00 , G06F16/9535 , G06F3/044 , H04B5/00
Abstract: A user device connected to an edge device, based on a touch of a user includes an electrode in touch with a body of the user, a human body communication module that receives a first signal from the edge device through the body and the electrode, an operation processing module that acquires identification information, location information, version information of the edge device, and time information at which the first signal is received, from the first signal, and a memory module that stores the identification information, the location information, the version information, and the time information, as part of life log information.
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公开(公告)号：US20170347150A1
公开(公告)日：2017-11-30
申请号：US15586742
申请日：2017-05-04
Inventor： Woojoo LEE , Sukho LEE , Kyung Jin BYUN , Sung Weon KANG
IPC: H04N21/443 , H04N21/234 , H04N21/45 , H04N21/61
CPC classification number: H04N21/4436 , H04N21/23418 , H04N21/23614 , H04N21/44 , H04N21/4516 , H04N21/6125
Abstract: Provided is a video providing system. The video providing system includes a memory configured to store device information of a display device, an analyzer configured to receive an original video from the outside and analyze images in the original video, and a processor configured to generate, from the original video, video streams according to a streaming mode and control signals of the display device respectively corresponding to the video streams, based on device information of a display device and analysis information from the analyzer, and provide the video streams and the control signals to the display device.
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公开(公告)号：US20210126716A1
公开(公告)日：2021-04-29
申请号：US17020400
申请日：2020-09-14
Inventor： Sung Eun KIM , Tae Wook KANG , Hyuk KIM , Kwang IL OH , Kyung Hwan PARK , Mi Jeong PARK , Hyung-IL PARK , Kyung Jin BYUN , Jae-Jin LEE , In Gi LIM
Abstract: A human body communication device includes an electrode, a matching circuit, a switch providing a first path electrically connected to the matching circuit and a second path electrically connected to the matching circuit, a sensor, in a first state, connected to the matching circuit through the switch, outputting a first sensing signal to the matching circuit, and outputting a second sensing signal when a difference between a signal generated from the matching circuit in response to the first sensing signal and the first sensing signal is greater than or equal to a threshold, a transmitter, in a second state, connected to the matching circuit through the switch, and outputting a data signal to the matching circuit, and a controller controlling the switch from the first state to the second state in response to receiving the second sensing signal from the sensor, in the first state.
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公开(公告)号：US20200295848A1
公开(公告)日：2020-09-17
申请号：US16816109
申请日：2020-03-11
Inventor： Tae Wook KANG , Sung Eun KIM , Kwang IL OH , Hyuk KIM , Mi Jeong PARK , Hyung-IL PARK , Kyung Jin BYUN , Jae-Jin LEE , In Gi LIM
Abstract: Provided are a human body communication device and an operating method of the same. The human body communication device according to an embodiment of the inventive concept includes a first electrode, a second electrode, a transmitting circuit, a receiving circuit, a ground electrode, and a switch. The transmitting circuit generates a first signal in a transmitting mode and transmits the first signal to the first electrode. The receiving circuit receives a second signal from the first electrode in the receiving mode. The receiving circuit includes a differential amplifier that amplifies a difference between a voltage level of a first input terminal depending on the second signal and a voltage level of a second input terminal. The switch electrically connects the second electrode and the ground electrode in the transmitting mode, and electrically connects the second electrode and the second input terminal in the receiving mode.
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公开(公告)号：US20200260957A1
公开(公告)日：2020-08-20
申请号：US16794718
申请日：2020-02-19
Inventor： Sung Eun KIM , Kwang IL OH , Tae Wook KANG , Hyuk KIM , Mi Jeong PARK , Hyung-IL PARK , Kyung Jin BYUN , Jae-Jin LEE , In Gi LIM
IPC: A61B5/00
Abstract: The human body sensing device includes a contact sensing unit that includes a sensing electrode and a signal electrode, an activation module that senses a contact with a body through the sensing electrode when the sensing electrode and the signal electrode contact the body and outputs a wake-up signal in response to the sensing of the contact, and a human body communication unit that provides a ground voltage to the signal electrode and outputs a data signal to the signal electrode when the wake-up signal from the activation module is received.
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Patent Agency Ranking
公开(公告)号：US20200259569A1
公开(公告)日：2020-08-13
申请号：US16784151
申请日：2020-02-06
Inventor： Kwang IL OH , Sung Eun KIM , Tae Wook KANG , Hyuk KIM , Mi Jeong PARK , Hyung-IL PARK , Kyung Jin BYUN , Jae-Jin LEE , In Gi LIM
Abstract: Provided is a receiver. The receiver according to the inventive concept includes a first filter circuit, a second filter circuit, and an amplifier. The first filter circuit provides a first path for first frequency components below first cutoff frequency of input frequency components and passes second frequency components except for the first frequency components of the input frequency components through second path. The second filter circuit attenuates third frequency components below a second cutoff frequency of the second frequency components. The amplifier amplifies the second frequency components including the attenuated third frequency components.
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公开(公告)号：US20170262011A1
公开(公告)日：2017-09-14
申请号：US15432588
申请日：2017-02-14
Inventor： Young-Su KWON , Kyung Jin BYUN , Nak Woong EUM
CPC classification number: G06F11/1608 , G06F1/06 , G06F1/12 , G06F11/0724 , G06F11/1641 , G06F11/1675 , G06F11/1679
Abstract: Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.
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公开(公告)号：US20170206102A1
公开(公告)日：2017-07-20
申请号：US15408210
申请日：2017-01-17
Inventor： Jae-Jin LEE , Hyeong Uk JANG , Kyung Jin BYUN , Nak Woong EUM
CPC classification number: G06F9/455 , G06F9/4451 , G06F17/30979 , G06F21/00 , G06F21/53 , G06F21/88
Abstract: An electronic device configured to perform forensic analysis on a target device includes a data extractor, an emulator, and a user data converter. The data extractor obtains, from the target device, a source file of at least one of applications installed on the target device. The data extractor obtains, from the target device, user data generated according to the least one of the applications being executed in the target device. The emulator emulates an execution of a target application installed based on the obtained source file. The user data converter converts the obtained user data having a data structure according to a database scheme of the target device into converted user data having a data structure according to a database scheme of the emulator. The emulator emulates the execution of the target application such that the target application operates using the converted user data.
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公开(公告)号：US20170192885A1
公开(公告)日：2017-07-06
申请号：US15222940
申请日：2016-07-28
Inventor： Jae-Jin LEE , Kyung Jin BYUN , Nak Woong EUM
IPC: G06F12/084 , G06F12/0875 , G06F9/30 , G06F12/0842
CPC classification number: G06F12/084 , G06F9/3017 , G06F12/0842 , G06F12/0875 , G06F17/5022 , G06F2212/452 , G06F2212/62 , G06F2217/68
Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.
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公开(公告)号：US20150006935A1
公开(公告)日：2015-01-01
申请号：US14300942
申请日：2014-06-10
Inventor： Jin Ho HAN , Young Su KWON , Kyoung Seon SHIN , Kyung Jin BYUN , Nak Woong EUM
IPC: G06F1/32
CPC classification number: G06F1/3275 , G06F1/3206 , G06F12/0864 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
Abstract: Disclosed are a processor capable of reducing power consumption of a cache by controlling power mode of the cache and a method for the same. A processor may comprise a processor core; a cache storing instructions to be executed in the processor core; and a cache management part controlling the cache based on a processor operation mode indicating a state of the processor core determined according to algorithm executed in the processor core. Thus, power consumption of cache may be reduced, and degradation of processor core performance may be prevented by controlling power mode of cache considering an operation mode of the processor.
Abstract translation: 公开了一种能够通过控制高速缓存的功率模式来降低高速缓存的功耗的处理器及其方法。 处理器可以包括处理器核心; 存储要在处理器核心中执行的指令的高速缓存; 以及高速缓存管理部，其基于指示根据在所述处理器核心中执行的算法确定的所述处理器核心的状态的处理器操作模式来控制所述高速缓存。 因此，可以降低高速缓存的功率消耗，并且可以通过考虑处理器的操作模式来控制高速缓存的功率模式来防止处理器核心性能的劣化。
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