利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

43 条记录 (耗时 0.049 秒)

    Low-swing bus driver and receiver
    22.
    发明申请
    Low-swing bus driver and receiver 有权
    低调总线驱动和接收器

    公开(公告)号：US20050148102A1

    公开(公告)日：2005-07-07

    申请号：US10748833

    申请日：2003-12-30

    申请人： Mark Anders ,  Peter Caputa ,  Ram Krishnamurthy

    发明人： Mark Anders ,  Peter Caputa ,  Ram Krishnamurthy

    IPC分类号： H01L21/00

    CPC分类号： H03K19/018521 ,  H03K3/356139 ,  H04L25/028 ,  H04L25/0292

    摘要： According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.

    摘要翻译： 根据一些实施例，提供了一种用于接收全摆幅输入信号，将全摆幅输入信号转换为低摆幅信号并传输低回转信号的静态低摆幅驱动器电路，以及动态 接收器电路来接收低摆动信号并将低摆幅信号转换成全摆幅信号。 还可以提供耦合到驱动器电路和接收器电路的互连，互连不包括中继器并且接收来自驱动器电路的低摆动信号并且将低回转信号发送到接收器电路。

    Encoder and decoder circuits for dynamic bus
    23.
    发明申请
    Encoder and decoder circuits for dynamic bus 有权
    用于动态总线的编码器和解码器电路

    公开(公告)号：US20050146357A1

    公开(公告)日：2005-07-07

    申请号：US10744084

    申请日：2003-12-24

    申请人： Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    发明人： Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC分类号： H03K19/0175 ,  H04L25/02

    CPC分类号： H04L25/0278 ,  H04L25/028

    摘要： A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

    摘要翻译： 提供动态总线架构。 这可以包括耦合到总线线路的编码电路和耦合到总线线路的解码器电路。 编码器电路可以接收输入信号并在总线上生成编码信号。 解码器电路可以从总线接收编码信号并产生原始未编码信号。 编码器电路可以包括第一触发器电路，其基于来自总线的时钟信号来存储来自总线的先前输入信号。 此外，解码器电路可以包括具有时钟输入的第二触发器电路，以从总线接收编码信号作为时钟输入。

    Browser and publisher for multimedia object storage, retrieval and transfer
    24.
    发明授权
    Browser and publisher for multimedia object storage, retrieval and transfer 失效
    浏览器和发布者用于多媒体对象的存储，检索和传输

    公开(公告)号：US06269403B1

    公开(公告)日：2001-07-31

    申请号：US08885065

    申请日：1997-06-30

    申请人： Mark Anders

    发明人： Mark Anders

    IPC分类号： H04H1218

    CPC分类号： H04L29/06 ,  H04L67/02 ,  H04L67/28 ,  H04L67/2833 ,  H04L69/04 ,  H04L69/14 ,  H04L69/22 ,  H04L69/329

    摘要： In a computer environment, a browser and publisher capable of exchanging multimedia objects provided in a new storage and delivery data format that increases performance and improves the user experience by reducing the transactions needed to retrieve a set of n objects from n to 1. The object data is interleaved with data definition entries identifying respective object data into a data format comprising a single stream for storage and/or delivery. The data format eliminates the need for multiple, asynchronous transactions thus reducing latency in the data transfer process. Moreover, the data format allows for optimization of how the object data is prioritized and interleaved to achieve desired performance objectives upon delivery of the multimedia objects for display using the browser.

    摘要翻译： 在计算机环境中，能够交换以新的存储和传送数据格式提供的多媒体对象的浏览器和发布者，该格式通过将从n到n的一组n对象所需的事务减少到1来提高性能并提高用户体验。该对象 数据与识别相应对象数据的数据定义条目交错为包括用于存储和/或传送的单个流的数据格式。 数据格式消除了对多个异步事务的需要，从而减少了数据传输过程中的延迟。 此外，数据格式允许在传送用于使用浏览器进行显示的多媒体对象的传送时优化对象数据的优先级和交织以实现期望的性能目标。

    Declarative Animation Timelines
    25.
    发明申请
    Declarative Animation Timelines 审中-公开
    声明性动画时间轴

    公开(公告)号：US20130132840A1

    公开(公告)日：2013-05-23

    申请号：US13036297

    申请日：2011-02-28

    申请人： Joaquin Cruz Blas, JR. ,  Mark Anders ,  James W. Doubek ,  Joshua Hatwich

    发明人： Joaquin Cruz Blas, JR. ,  Mark Anders ,  James W. Doubek ,  Joshua Hatwich

    IPC分类号： G06F3/01

    CPC分类号： G06T13/00 ,  G06T2213/08

    摘要： Methods and systems for declarative animation timelines are disclosed. In some embodiments, a method includes generating a declarative timeline data structure, creating an animation of an image along the timeline, and adding a declarative command corresponding to the animation into the declarative data structure. The method also includes, in response to a request to render the animation, generating a run-time command corresponding to the declarative command and executing the run-time command. In other embodiments, a method includes receiving a request to render an animation, wherein the animation includes a declarative timeline data structure having a plurality of commands, parsing the plurality of commands, passing each of the parsed plurality of commands to an animation function, receiving a plurality of run-time commands in response to said passing, and causing a rendering the animation by causing an execution of the plurality of run-time commands.

    摘要翻译： 公开了用于声明性动画时间线的方法和系统。 在一些实施例中，一种方法包括生成声明性时间轴数据结构，沿时间线创建图像的动画，以及将与动画对应的声明性命令添加到声明性数据结构中。 该方法还响应于呈现动画的请求，生成与声明性命令相对应的运行时命令并执行运行时命令。 在其他实施例中，一种方法包括接收呈现动画的请求，其中动画包括具有多个命令的声明性时间轴数据结构，解析多个命令，将所解析的多个命令中的每一个传递给动画功能，接收 响应于所述通过的多个运行时命令，并且通过引起多个运行时命令的执行而导致动画呈现。

    User interfaces, methods, and systems for developing computer applications using artwork
    26.
    发明授权
    User interfaces, methods, and systems for developing computer applications using artwork 有权
    使用艺术品开发计算机应用程序的用户界面，方法和系统

    公开(公告)号：US08417728B1

    公开(公告)日：2013-04-09

    申请号：US12242052

    申请日：2008-09-30

    申请人： Mark Anders ,  Adam Cath ,  Narciso B. Jaramillo ,  Allan Padgett

    发明人： Mark Anders ,  Adam Cath ,  Narciso B. Jaramillo ,  Allan Padgett

    IPC分类号： G06F7/00 ,  G06F17/30 ,  G06F12/00 ,  G06F15/16 ,  G06F3/048

    CPC分类号： G06F8/38 ,  G06F8/34 ,  G06Q10/06

    摘要： Methods and systems for using artwork to develop computer applications in ways that preserve the artwork's appearance and layout, including by importing the artwork and selectively replacing potions with functional components. One embodiment comprises a method for developing an application that involves displaying artwork in a design view area. The method may involve displaying artwork comprising a list representation comprising a plurality of list item representations and identifying each list item representation as a group of one or more subitem representations. The method may further comprise determining a list layout for list items using the list item representations of the artwork and inserting a list as a component in the design view area. This list may determine or otherwise be used to determine the positions of either the list item representations or list items replacing the list item representations. These positions may be determined based on the list layout that was determined.

    摘要翻译： 使用艺术品开发计算机应用程序的方法和系统，以保持艺术品的外观和布局，包括通过导入艺术品并用功能组件选择性地替换药水。 一个实施例包括用于开发涉及在设计视图区域中显示艺术品的应用的方法。 该方法可以包括显示包括包括多个列表项表示的列表表示的图形，并将每个列表项表示识别为一个或多个子项表示的组。 该方法可以进一步包括使用艺术品的列表项表示来确定列表项的列表布局，并将列表作为组件插入到设计视图区域中。 该列表可以确定或以其他方式用于确定替换列表项表示的列表项表示或列表项的位置。 这些位置可以基于确定的列表布局来确定。

    Transition encoded dynamic bus circuit
    28.
    发明授权
    Transition encoded dynamic bus circuit 有权
    转换编码动态总线电路

    公开(公告)号：US07161992B2

    公开(公告)日：2007-01-09

    申请号：US10035574

    申请日：2001-10-18

    申请人： Mark Anders ,  Ram Krishnamurthy

    发明人： Mark Anders ,  Ram Krishnamurthy

    IPC分类号： H03K9/00

    CPC分类号： H04L25/493 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/14

    摘要： A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. The decoder circuit decodes the transition encoded information to track the appropriate value to be output from the bus.

    摘要翻译： 转换编码的动态总线包括总线输入端的编码器电路和总线输出端的解码器电路。 编码器电路产生指示在总线的输入处的转变而不是输入端的实际值的信号。 解码器电路解码转换编码信息以跟踪从总线输出的适当值。

    Data converter and a delay threshold comparator
    29.
    发明申请
    Data converter and a delay threshold comparator 失效
    数据转换器和延迟阈值比较器

    公开(公告)号：US20060221724A1

    公开(公告)日：2006-10-05

    申请号：US11094811

    申请日：2005-03-31

    申请人： Atul Maheshwari ,  Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy

    发明人： Atul Maheshwari ,  Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy

    IPC分类号： G11C7/06

    CPC分类号： G06F9/3869 ,  G06F7/74

    摘要： For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.

    摘要翻译： 对于一个所公开的实施例，转换器将2个N位数据转换为指示具有预定逻辑值的数据中的位数的N位值。 转换器包括N个比较器，每个比较器确定具有预定逻辑值的数据中的位数是否超过多个参考值中的相应一个。 基于比较器的输出产生N位值。 对于另一个公开的实施例，第一延迟元件基于具有预定逻辑值的数据值中的位数来延迟信号，并且第二延迟元件基于具有预定逻辑的参考值中的位数来延迟该信号 值。 比较器然后基于延迟信号产生位值。