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21.发明授权
公开(公告)号：US6002152A
公开(公告)日：1999-12-14
申请号：US207956
申请日：1998-12-09
IPC分类号： G11C11/56 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , H01L27/115 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译： 新型存储单元利用源侧注入，允许非常小的编程电流。 如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。 在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。 在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。 在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于 后续写操作。 在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。 如果所有待编程的单元都已被正确编程，则位线电流将基本为零。 如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。 重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。
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公开(公告)号：US5883409A
公开(公告)日：1999-03-16
申请号：US908744
申请日：1997-08-07
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C11/5635 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
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公开(公告)号：US20100169559A1
公开(公告)日：2010-07-01
申请号：US12723491
申请日：2010-03-12
CPC分类号： G06F13/4068 , G06K19/07741 , H05K5/0265 , H05K5/0282
摘要： A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.
摘要翻译： 具有个人计算机（“PC”）卡形状因子并且可拆卸地耦合到主机系统外部的外围卡进一步被划分为母卡部分和子卡部分。 子卡可拆卸地耦合到母卡。 在优选实施例中，低成本闪存“软盘”是通过仅包含快闪EEPROM芯片的子卡并由驻留在母卡上的存储器控制器来控制的。 本发明的其它方面包括：母卡上的综合控制器，其能够控制可连接到母卡的子卡上的预定义的一组外围设备; 将一些主机驻地硬件重定位到母卡以允许最小的主机系统; 可容纳多张子卡的母卡; 子卡也直接与具有嵌入式控制器的主机操作; 携带编码数据的子卡和用于解码的信息; 和具有安全功能的子卡。
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公开(公告)号：US07449746B2
公开(公告)日：2008-11-11
申请号：US11278778
申请日：2006-04-05
IPC分类号： H01L29/94
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0458 , G11C16/0491 , H01L27/115 , H01L29/7881
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译： 新型存储单元利用源侧注入，允许非常小的编程电流。 如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。 在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。 在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。 在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于 后续写操作。 在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。 如果所有待编程的单元都已被正确编程，则位线电流将基本为零。 如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。 重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。
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25.发明授权公开(公告)号：US07071060B1
公开(公告)日：2006-07-04
申请号：US09386170
申请日：1999-08-31
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0458 , G11C16/0491 , H01L27/115 , H01L29/7881
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译： 新型存储单元利用源侧注入，允许非常小的编程电流。 如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。 在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。 在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。 在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于 后续写操作。 在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。 如果所有待编程的单元都已被正确编程，则位线电流将基本为零。 如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。 重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。
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公开(公告)号：US06893268B1
公开(公告)日：2005-05-17
申请号：US10841370
申请日：2004-05-06
CPC分类号： G06F13/4068 , G06K19/07741 , H05K5/0265 , H05K5/0282
摘要： A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.
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公开(公告)号：US5847996A
公开(公告)日：1998-12-08
申请号：US639128
申请日：1996-04-26
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译： 新型存储单元利用源侧注入，允许非常小的编程电流。 如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。 在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。 在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。 在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于 后续写操作。 在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。 如果所有待编程的单元都已被正确编程，则位线电流将基本为零。 如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。 重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。
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公开(公告)号：US5369615A
公开(公告)日：1994-11-29
申请号：US149602
申请日：1993-11-08
CPC分类号： G11C16/10 , G11C16/16 , G11C16/26 , G06F11/1008
摘要： Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM), An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses, Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single- and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group, Defects handling includes an adaptive data encoding scheme.
摘要翻译： 各种优化技术用于擦除半导体电可擦除可编程只读存储器（EEPROM），擦除算法通过应用增量擦除脉冲来实现擦除一组存储器单元。技术包括脉冲应用之间的两相验证过程交错; 对每个可擦除单元组内的单元格样本进行特殊处理; 缺陷处理; 自适应初始擦除电压; 以及通过表查找具有扇区到扇区估计擦除特性的单和混合相位算法。 还采用技术来控制每个可擦除单元组中的单元的编程/擦除循环的均匀性，缺陷处理包括自适应数据编码方案。
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公开(公告)号：US5270979A
公开(公告)日：1993-12-14
申请号：US670246
申请日：1991-03-15
CPC分类号： G11C16/10 , G11C16/16 , G11C16/26 , G06F11/1008
摘要： Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single-and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group. Defects handling includes an adaptive data encoding scheme.
摘要翻译： 各种优化技术用于擦除半导体电可擦除可编程只读存储器（EEPROM）。 擦除算法通过应用增量擦除脉冲来实现一组存储器单元的擦除。 技术包括脉冲应用之间的两相验证过程交错; 对每个可擦除单元组内的单元格样本进行特殊处理; 缺陷处理; 自适应初始擦除电压; 以及通过表查找对扇区到扇区估计擦除特性的单和混合相位算法。 还采用技术来控制每个可擦除单元组中的单元的编程/擦除循环的均匀性。 缺陷处理包括自适应数据编码方案。
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公开(公告)号：US5910925A
公开(公告)日：1999-06-08
申请号：US65409
申请日：1998-04-23
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： A novel memory structure in which memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.
摘要翻译： 一种新颖的存储器结构，其中存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列形成。 在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。 在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于 后续写操作。
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