公开(公告)号：US06399433B2

公开(公告)日：2002-06-04

申请号：US09773218

申请日：2001-01-31

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/55

摘要： A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.

摘要翻译： 一种存储单元的制造方法包括在半导体本体上形成多晶硅层，该多晶硅层具有设置在第一平面中的至少一个选择晶体管。 在层的两个相邻结构之间形成间隙，并且该层的相邻结构之一被放置在第一硅插头的表面上。 在该间隙中形成单元板电极，并在该层中形成沟槽。 沟槽达到第一插头表面的最远处，并且填充有绝缘层。 该层被删除。 形成具有高ε或铁电介质的存储电容器和存储节点电极。 电容器设置在身体内和上方的第二平面内。 绝缘层被硅替代以形成直接连接到第一插头的第二硅插头。 第二插头电连接到存储节点电极，第一平面通过第一和第二插头电连接到第二平面。

公开(公告)号：US06265748B1

公开(公告)日：2001-07-24

申请号：US09180129

申请日：1998-11-02

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Josef Willer

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Josef Willer

IPC分类号： H01L2976

CPC分类号： H01L27/112 ,  G11C11/5692 ,  H01L27/11273

摘要： A memory cell arrangement, and method for producing same, which includes vertical MOS transistors as memory cells wherein the information is stored by means of at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is obtained by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are obtained by different channel dopings. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).

摘要翻译： 一种存储单元布置及其制造方法，其包括作为存储单元的垂直MOS晶体管，其中通过多级编程通过晶体管的至少三个不同的阈值电压值来存储信息。 通过厚氧化物晶体管的栅极电介质的厚度获得一个阈值电压值，并且通过不同的沟道掺杂获得其它阈值电压值。 可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。

公开(公告)号：US06242319B1

公开(公告)日：2001-06-05

申请号：US09498530

申请日：2000-02-04

申请人： Franz Hofmann ,  Josef Willer

发明人： Franz Hofmann ,  Josef Willer

IPC分类号： H01L2176

CPC分类号： H01L27/10858 ,  H01L23/544 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first structure of a circuit configuration and a first alignment structure are produced in the region of a surface of a first substrate. The first alignment structure scatters electron beams differently than its surroundings. A second substrate, which is more transmissive to electron beams than the first alignment structure, is connected to the first substrate in such a way that the second substrate is disposed above the surface of the first substrate. In order to align a mask with respect to the first structure, a position of the first alignment structure is determined with the aid of electron beams. With the aid of the mask, at least one second structure of the circuit configuration is produced in the region of an uncovered upper surface of the second substrate. The first structure may be a metallic line encapsulated by insulating material. A contact may connect the first structure to the second structure. With the aid of electron beam lithography, at least one second alignment structure may be produced in the region of the upper surface of the second substrate, using which the mask is aligned.

摘要翻译： 在第一基板的表面的区域中制造电路结构和第一对准结构的第一结构。 第一对准结构与其周围环境不同地散射电子束。 与第一对准结构相比，对电子束更透射的第二衬底以这样的方式连接到第一衬底，使得第二衬底设置在第一衬底的表面之上。 为了使掩模相对于第一结构对准，借助于电子束来确定第一对准结构的位置。 借助于掩模，在第二基板的未覆盖的上表面的区域中产生电路构造的至少一个第二结构。 第一结构可以是由绝缘材料包封的金属线。 触点可以将第一结构连接到第二结构。 借助于电子束光刻技术，可以在第二衬底的上表面的区域中产生至少一个第二对准结构，使用掩模进行对准。

公开(公告)号：US07778073B2

公开(公告)日：2010-08-17

申请号：US11872655

申请日：2007-10-15

申请人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

发明人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/11568

摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

摘要翻译： 本发明的实施例一般涉及用于制造集成电路的集成电路和方法。 在本发明的实施例中，提供了具有存储单元的集成电路。 存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区 旁边的沟槽。

公开(公告)号：US06608340B1

公开(公告)日：2003-08-19

申请号：US09821853

申请日：2001-03-30

申请人： Franz Hofmann ,  Till Schlösser ,  Josef Willer

发明人： Franz Hofmann ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L2972

CPC分类号： H01L27/10864

摘要： A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main surface, is provided with at least one corner. A cross-section of the lower area, parallel to the main surface, matches the cross-section of the upper area, particularly in the vicinity the upper area, with the following difference: each corner is rounded, whereby the cross section of the lower area is smaller than the cross-section of the upper area. In order to produce the indentation, the upper area is provided with an auxiliary spacer that is rounded by isotropic etching. The lower area is produced by selectively etching the substrate to form an auxiliary spacer.

摘要翻译： 凹陷从基板的主表面延伸到所述基板的内部，并且具有上部区域和相邻的下部区域。 平行于主表面的上部区域的横截面设置有至少一个角部。 平行于主表面的下部区域的横截面与上部区域的横截面特别是在上部区域附近匹配，具有以下差异：每个角都是圆形的，由此下部区域的横截面 面积小于上部区域的横截面。 为了产生凹陷，上部区域设置有通过各向同性蚀刻而被圆化的辅助间隔件。 通过选择性地蚀刻基板以形成辅助间隔物来产生下部区域。

公开(公告)号：US06599797B1

公开(公告)日：2003-07-29

申请号：US09980811

申请日：2002-03-11

申请人： Franz Hofmann ,  Josef Willer

发明人： Franz Hofmann ,  Josef Willer

IPC分类号： H01L218242

CPC分类号： H01L27/10873 ,  H01L27/10888 ,  H01L27/1203

摘要： The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO2 layer (O). An upper part of said recess (V) which is located in the range of the silicon layer (S) has cylindrical shape with a horizontal first cross-section. A lower part of the recess (V) which is located in the range of the SiO2 layer (O), compared with the upper part of the recess (V), is bulged to such an extent that it has a cylindrical shape with a horizontal second cross-section that is larger than the first cross-section. A cylinder (Z) of an insulating material is provided in the recess (V). The horizontal cross-section of said cylinder corresponds to the first cross-section and the lower part thereof is located in the lower part of the recess (V). The dent laterally surrounds the lower part of the cylinder (Z). A conducting structure (L) is located in the dent and adjoins the silicon layer (S) and the silicon substrate (1) so that the channel zone of the MOS transistors is electrically connected to the silicon substrate.

摘要翻译： 本发明涉及一种SOI衬底，其具有穿过硅层和SiO 2层（O）的凹部。 位于硅层（S）的范围内的所述凹部（V）的上部具有水平的第一横截面的圆筒形状。 与凹部（V）的上部相比，位于SiO 2层（O）的范围内的凹部（V）的下部被凸出到具有水平的圆筒形状的程度 第二横截面大于第一横截面。 在凹部（V）中设置绝缘材料的圆筒（Z）。 所述气缸的水平截面对应于第一横截面，其下部位于凹部（V）的下部。 凹陷横向围绕气缸（Z）的下部。 导电结构（L）位于凹陷中并与硅层（S）和硅衬底（1）相邻，使得MOS晶体管的沟道区电连接到硅衬底。

公开(公告)号：US6125050A

公开(公告)日：2000-09-26

申请号：US335365

申请日：1999-06-17

申请人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Paul-Werner Basse ,  Wolfgang Krautschneider

发明人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Paul-Werner Basse ,  Wolfgang Krautschneider

IPC分类号： H01L27/112 ,  G11C5/02 ,  H01L21/8246

CPC分类号： H01L27/0207 ,  H01L27/1126 ,  H01L27/11293 ,  H01L27/11803

摘要： Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.

摘要翻译： 平行线，例如由半导体衬底中的掺杂区形成的存储单元配置中的位线，通过将多个线彼此电连接并连接到公共节点来驱动。 多条选择线横向延伸。 MOS晶体管布置在交点处，并沿着一条线串联连接。 MOS晶体管的栅电极由相应的选择线形成。 每条并行线路中的至少一个MOS晶体管的阈值电压高于其他。

公开(公告)号：US07772580B2

公开(公告)日：2010-08-10

申请号：US11837380

申请日：2007-08-10

申请人： Franz Hofmann ,  Josef Willer

发明人： Franz Hofmann ,  Josef Willer

IPC分类号： H01L29/02

CPC分类号： H01L45/149 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1683

摘要： In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure.

摘要翻译： 在本发明的实施例中，提供了具有单元的集成电路。 电池可以包括场效应晶体管结构，其包括设置在栅极堆叠上方的栅极堆叠和电阻率变化材料结构，其中电阻率变化材料结构包括电阻率变化材料，其被配置为响应于应用 对电阻率变化材料结构的电压。

公开(公告)号：US06492221B1

公开(公告)日：2002-12-10

申请号：US09806427

申请日：2001-07-03

申请人： Franz Hofmann ,  Josef Willer ,  Till Schloesser

发明人： Franz Hofmann ,  Josef Willer ,  Till Schloesser

IPC分类号： H01L218244

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876

摘要： A dynamic random access memory includes memory cells arranged in rows and columns on the substrate and a plurality of connecting pillars, each associated with a memory cell. A bit line extends above the main area of the substrate and connects to each memory cell of a column. A first word line connects a first set of alternate memory cells of a row by a first subset of the plurality of connecting pillars. The first word line includes first parts arranged offset relative to the first subset of connecting pillars. A strip-shaped second part extends above the main area and adjoins the first parts of the first word line. A second word line connects to a second set of alternate memory cells of the row by a second subset of the connecting pillars. The second word line includes first parts arranged between mutually adjacent first word lines and offset from the second subset of the connecting pillars. Both the first and second word lines thus overlap but do not cover the connecting pillars. A strip-shaped second part extends above the main area in the first direction and adjoins the first parts of the second word line. The second part is above the first word line and the bit line.

摘要翻译： 动态随机存取存储器包括以衬底上的行和列布置的存储器单元和多个连接柱，每个连接柱与存储单元相关联。 位线延伸到基板的主区域上方，并连接到列的每个存储单元。 第一字线将一行的第一组备用存储单元与多个连接柱的第一子集连接。 第一字线包括相对于连接柱的第一子集排列的第一部分。 带状第二部分在主区域的上方延伸并与第一字线的第一部分邻接。 第二字线通过连接柱的第二子集连接到该行的第二组替代存储器单元。 第二字线包括布置在彼此相邻的第一字线之间的第一部分和与连接柱的第二子集的偏移。 因此，第一和第二字线都重叠，但不覆盖连接柱。 带状第二部分沿着第一方向延伸到主区域上方并与第二字线的第一部分相邻。 第二部分在第一个字线和位线之上。

公开(公告)号：US06448600B1

公开(公告)日：2002-09-10

申请号：US09713484

申请日：2000-11-15

申请人： Till Schlösser ,  Franz Hofmann ,  Josef Willer

发明人： Till Schlösser ,  Franz Hofmann ,  Josef Willer

IPC分类号： H01L218242

CPC分类号： H01L27/10867 ,  H01L27/10876 ,  H01L27/10888

摘要： The memory cells each have a capacitor and a transistor. A storage node of the capacitor is arranged in a first depression formed in a substrate. A gate electrode of the transistor is arranged in a second depression at a first lateral surface of the second depression. The second depression is spaced apart from the first depression. An upper source/drain region of the transistor adjoins the storage node and the second depression. A lower source/drain region of the transistor is formed deeper in the substrate than the upper source/drain region and it adjoins the second depression.

摘要翻译： 存储单元各自具有电容器和晶体管。 电容器的存储节点布置在形成在基板中的第一凹部中。 晶体管的栅极布置在第二凹陷处的第二凹陷处的第二凹陷处的第一侧表面处。 第二凹陷与第一凹陷间隔开。 晶体管的上源极/漏极区域与存储节点和第二凹陷相邻。 晶体管的下源极/漏极区域在衬底中比上部源极/漏极区域形成得更深，并且与第二凹陷相邻。