公开(公告)号：US06576948B2

公开(公告)日：2003-06-10

申请号：US09873231

申请日：2001-06-04

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L27108

CPC分类号： H01L27/108

摘要： An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.

摘要翻译： 集成电路包含平面第一晶体管和二极管。 二极管连接在第一晶体管的第一源极/漏极区域和第一晶体管的栅电极之间，使得电荷被阻止从栅电极放电到第一源极/漏极区域。 作为二极管的一部分的二极管层设置在第一源极/漏极区域的一部分上。 作为二极管的附加部分的导电结构设置在栅电极的一部分上方并且设置在二极管层上。 二极管可以配置为隧道二极管。 二极管层可以通过热氧化生产。 制造二极管只需要一个掩模。 电容器可以设置在二极管的上方。 电容器的第一电容器电极连接到导电结构。

公开(公告)号：US06608340B1

公开(公告)日：2003-08-19

申请号：US09821853

申请日：2001-03-30

申请人： Franz Hofmann ,  Till Schlösser ,  Josef Willer

发明人： Franz Hofmann ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L2972

CPC分类号： H01L27/10864

摘要： A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main surface, is provided with at least one corner. A cross-section of the lower area, parallel to the main surface, matches the cross-section of the upper area, particularly in the vicinity the upper area, with the following difference: each corner is rounded, whereby the cross section of the lower area is smaller than the cross-section of the upper area. In order to produce the indentation, the upper area is provided with an auxiliary spacer that is rounded by isotropic etching. The lower area is produced by selectively etching the substrate to form an auxiliary spacer.

摘要翻译： 凹陷从基板的主表面延伸到所述基板的内部，并且具有上部区域和相邻的下部区域。 平行于主表面的上部区域的横截面设置有至少一个角部。 平行于主表面的下部区域的横截面与上部区域的横截面特别是在上部区域附近匹配，具有以下差异：每个角都是圆形的，由此下部区域的横截面 面积小于上部区域的横截面。 为了产生凹陷，上部区域设置有通过各向同性蚀刻而被圆化的辅助间隔件。 通过选择性地蚀刻基板以形成辅助间隔物来产生下部区域。

公开(公告)号：US06399433B2

公开(公告)日：2002-06-04

申请号：US09773218

申请日：2001-01-31

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/55

摘要： A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.

摘要翻译： 一种存储单元的制造方法包括在半导体本体上形成多晶硅层，该多晶硅层具有设置在第一平面中的至少一个选择晶体管。 在层的两个相邻结构之间形成间隙，并且该层的相邻结构之一被放置在第一硅插头的表面上。 在该间隙中形成单元板电极，并在该层中形成沟槽。 沟槽达到第一插头表面的最远处，并且填充有绝缘层。 该层被删除。 形成具有高ε或铁电介质的存储电容器和存储节点电极。 电容器设置在身体内和上方的第二平面内。 绝缘层被硅替代以形成直接连接到第一插头的第二硅插头。 第二插头电连接到存储节点电极，第一平面通过第一和第二插头电连接到第二平面。

公开(公告)号：US06448600B1

公开(公告)日：2002-09-10

申请号：US09713484

申请日：2000-11-15

申请人： Till Schlösser ,  Franz Hofmann ,  Josef Willer

发明人： Till Schlösser ,  Franz Hofmann ,  Josef Willer

IPC分类号： H01L218242

CPC分类号： H01L27/10867 ,  H01L27/10876 ,  H01L27/10888

摘要： The memory cells each have a capacitor and a transistor. A storage node of the capacitor is arranged in a first depression formed in a substrate. A gate electrode of the transistor is arranged in a second depression at a first lateral surface of the second depression. The second depression is spaced apart from the first depression. An upper source/drain region of the transistor adjoins the storage node and the second depression. A lower source/drain region of the transistor is formed deeper in the substrate than the upper source/drain region and it adjoins the second depression.

摘要翻译： 存储单元各自具有电容器和晶体管。 电容器的存储节点布置在形成在基板中的第一凹部中。 晶体管的栅极布置在第二凹陷处的第二凹陷处的第二凹陷处的第一侧表面处。 第二凹陷与第一凹陷间隔开。 晶体管的上源极/漏极区域与存储节点和第二凹陷相邻。 晶体管的下源极/漏极区域在衬底中比上部源极/漏极区域形成得更深，并且与第二凹陷相邻。

公开(公告)号：US06442065B1

公开(公告)日：2002-08-27

申请号：US09935356

申请日：2001-08-22

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

IPC分类号： G11C1140

CPC分类号： G11C11/404 ,  G11C11/4023

摘要： Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.

摘要翻译： 单元结构的每个存储单元包括至少一个存储晶体管。 为了在存储单元上写入第一或第二信息，对存储晶体管的栅电极进行充电，使得在存储晶体管中施加第一电压或第二电压。 在存储晶体管的第二源极/漏极区域中施加读取电压以分别读取第一信息和第二信息。 第一电压施加在第二电压和读取电压之间。 读取电压施加在较低存储晶体管的阈值电压的第一电压和小于存储晶体管的阈值电压的第二电压之间。

公开(公告)号：US07368752B2

公开(公告)日：2008-05-06

申请号：US10839800

申请日：2004-05-06

申请人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

发明人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

IPC分类号： H01L27/108 ,  H01L29/12 ,  H01L31/112

CPC分类号： H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

摘要： A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

摘要翻译： DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层 在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器， 所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

公开(公告)号：US06566193B2

公开(公告)日：2003-05-20

申请号：US10096473

申请日：2002-03-12

申请人： Franz Hofmann ,  Till Schlösser

发明人： Franz Hofmann ,  Till Schlösser

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10876

摘要： The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the conductive trench fill. The first insulating layer is then overgrown laterally by a selectively grown epitaxial layer. The selective epitaxial layer is so structured that a ridge is formed from it. Next, the ridge is partially undercut, whereby the etch selectivity of the ridge relative to the first insulating layer is utilized for a wet-chemical etching procedure. Next, a contact layer is arranged in the undercut region, which connects the ridge and a transistor that has been formed in the ridge to the conductive trench fill. Lateral margin ridges are then formed next to the ridge as a gate, and a doped region is incorporated into the ridge as a source/drain zone of the transistor.

公开(公告)号：US06534820B2

公开(公告)日：2003-03-18

申请号：US09745565

申请日：2000-12-21

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser

IPC分类号： H01L29788

CPC分类号： H01L27/10844 ,  H01L27/108 ,  H01L27/10876

摘要： An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate connection area that is connected to a word line, a source connection doping area which is connected to a bit line, and a drain connection doping area. A memory MOSFET has a gate connection area which is connected via a thin dielectric layer to a connection doping region which connects a source connection doping area of the memory MOSFET to the drain connection doping area of the selection MOSFET. The memory MOSFET further has a drain connection doping area that is connected to a supply voltage. The selection and memory MOSFETs are disposed on opposite sidewalls of a trench, which is etched in the substrate, and the connection doping region forms a bottom of the trench.

摘要翻译： 描述在半导体衬底上具有小面积范围的集成动态存储单元。 存储单元具有选择MOSFET，其具有连接到字线的栅极连接区域，连接到位线的源极连接掺杂区域和漏极连接掺杂区域。 存储器MOSFET具有通过薄介电层连接到将存储器MOSFET的源极连接掺杂区域连接到选择MOSFET的漏极连接掺杂区域的连接掺杂区域的栅极连接区域。 存储器MOSFET还具有连接到电源电压的漏极连接掺杂区域。 选择和存储器MOSFET被布置在沟槽的相对的侧壁上，沟槽被蚀刻在衬底中，并且连接掺杂区域形成沟槽的底部。

公开(公告)号：US06274453B1

公开(公告)日：2001-08-14

申请号：US09405916

申请日：1999-09-24

申请人： Till Schlösser ,  Franz Hofmann ,  Wolfgang Krautschneider

发明人： Till Schlösser ,  Franz Hofmann ,  Wolfgang Krautschneider

IPC分类号： H01L2120

CPC分类号： H01L27/10876 ,  H01L27/10805 ,  H01L27/10808

摘要： A memory cell configuration with many ferroelectric or dynamic memory cells provided in a semiconductor substrate. Alternating trenches and lands extend parallel in a longitudinal direction of a main face of the semiconductor substrate. A channel stop layer is buried in the lands and divides the semiconductor substrate into a lower region that includes the trench bottoms and an upper region that includes the land ridges. First planar selection transistors with intervening trench channel stop regions are disposed along the trench bottoms. Second planar selection transistors with intervening land channel stop regions are disposed along the land ridges. The first and second selection transistors have respective source, gate, channel and drain regions, which are offset longitudinally from one another such that source and drain regions of the first and second selection transistors alternate in the transverse direction in the main face of the semiconductor substrate. Isolated word lines are provided which extend in the transverse direction along the main face for triggering the first and second selection transistors in the respective gate regions. Isolated bit lines are provided which extend in an oblique direction along the main face for connecting the first and second selection transistors in the respective source regions. And preferably ferroelectric capacitors are each connected to the drain regions of applicable selection transistors via capacitor contacts.

摘要翻译： 具有设置在半导体衬底中的许多铁电或动态存储单元的存储单元配置。 交替沟槽和焊盘在半导体衬底的主面的纵向方向上平行延伸。 沟道阻挡层埋在焊盘中，并将半导体衬底分成包括沟槽底部的下部区域和包括焊盘脊的上部区域。 具有中间沟槽沟道阻挡区域的第一平面选择晶体管沿沟槽底部设置。 具有中间的槽脊通道停止区域的第二平面选择晶体管沿着脊脊布置。 第一和第二选择晶体管具有各自的源极，栅极，沟道和漏极区域，它们彼此纵向偏移，使得第一和第二选择晶体管的源极和漏极区域在半导体衬底的主面中在横向方向上交替 。 提供隔离的字线，其沿着主面沿横向方向延伸，用于触发各个栅极区域中的第一和第二选择晶体管。 提供了沿着主面沿倾斜方向延伸的隔离位线，用于连接各个源极区域中的第一和第二选择晶体管。 并且优选地，铁电电容器通过电容器触点连接到适用的选择晶体管的漏极区域。

公开(公告)号：US06438022B2

公开(公告)日：2002-08-20

申请号：US09854259

申请日：2001-05-10

申请人： Till Schlösser ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas-Peter Haneder

发明人： Till Schlösser ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas-Peter Haneder

IPC分类号： G11C1122

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11507

摘要： The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.

摘要翻译： 存储单元结构的存储单元分别具有选择晶体管，存储晶体管和铁电电容器。 选择晶体管和存储晶体管串联连接。 铁电电容器连接在存储晶体管的控制电极和选择晶体管的第一端子之间。