Method of operating a storage cell arrangement
    2.
    发明授权
    Method of operating a storage cell arrangement 失效
    操作存储单元布置的方法

    公开(公告)号:US6040995A

    公开(公告)日:2000-03-21

    申请号:US230614

    申请日:1999-01-28

    摘要: For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

    摘要翻译: PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102(e)1999年1月28日PCT PCT 1997年7月29日PCT公布。 出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作,作为包含具有第一氧化硅层(51)的介电三层(5)的存储单元,具有氮化硅层(52)和第二氧化硅 层(53)作为栅极电介质,由此氧化硅层​​分别为至少3nm厚,将第一截止电压值分配给第一逻辑值,并将MOS晶体管的第二截止电压值分配给第二逻辑值 用于存储数字数据。 存储在存储单元中的信息可以通过施加相应的电压电平来修改,尽管由于氧化硅层的厚度,不可能完全去除存储在氮化硅层中的电荷。 当修改截止电压时,利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。

    Method for manufacturing an electrically writeable and erasable
read-only memory cell arrangement
    3.
    发明授权
    Method for manufacturing an electrically writeable and erasable read-only memory cell arrangement 失效
    用于制造电可写和可擦除的只读存储单元布置的方法

    公开(公告)号:US5882969A

    公开(公告)日:1999-03-16

    申请号:US967419

    申请日:1997-11-11

    摘要: In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS transistors are arranged in rows that run parallel. Adjacent rows thus respectively run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches. The control gates laterally surround the floating gates so that the memory cells on the bottom of the longitudinal trenches also comprise a coupling ratio>1. A surface requirement per memory cell of 2F.sup.2 (F minimum structural size) is achieved.

    摘要翻译: 在通过自调整处理步骤制造电可写和可擦除的仅ad的存储单元布置的方法中,制造了具有分别包括具有浮置栅极的MOS晶体管的存储单元的只读存储单元布置。 MOS晶体管排列成并行的行。 因此,相邻的行分别在纵向沟槽的底部和相邻的纵向沟槽之间交替地行进。 控制门横向围绕浮动栅极,使得纵向沟槽底部的存储单元也包括耦合比> 1。 实现2F2(F最小结构尺寸)每个存储单元的表面要求。

    Electrically programmable memory cell array, using charge carrier traps and insulation trenches
    5.
    发明授权
    Electrically programmable memory cell array, using charge carrier traps and insulation trenches 失效
    电可编程存储单元阵列,使用电荷载流子阱和绝缘沟槽

    公开(公告)号:US06191459B1

    公开(公告)日:2001-02-20

    申请号:US08780488

    申请日:1997-01-08

    IPC分类号: H01L2976

    摘要: An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of striplike, parallel insulation trenches. The width and spacing of the insulation trenches are preferably identical. The space required per memory cell of the memory cell array is 2F2, where F is the minimum structural size in the technology employed. The memory cells are programmed by selectively injecting electrons into the gate dielectric.

    摘要翻译: 电可编程存储单元阵列由包括垂直MOS晶体管的存储单元形成。 MOS晶体管具有具有电荷载流子阱的材料的栅极电介质。 存储单元沿带状平行绝缘沟槽的相对边缘设置。 绝缘沟槽的宽度和间距优选相同。 存储单元阵列每个存储单元所需的空间为2F2,其中F为所采用技术中的最小结构尺寸。 通过选择性地将电子注入到栅极电介质中来对存储器单元进行编程。

    Method for the manufacturing a memory cell configuration
    6.
    发明授权
    Method for the manufacturing a memory cell configuration 失效
    制造存储单元配置的方法

    公开(公告)号:US6153475A

    公开(公告)日:2000-11-28

    申请号:US331495

    申请日:1999-06-21

    CPC分类号: H01L27/112

    摘要: For the manufacture of a memory cell arrangement with first memory cells that comprise a vertical MOS transistor and with second memory cells that do not comprise an MOS transistor, whereby the memory cells are arranged along opposite edges of strip-type trenches, memory cells that are adjacent along the trenches (5) are manufactured successively. The spacing of adjacent memory cells is determined in particular by means of a spacer technology. By this means, a space requirement per memory cell of 1F.sup.2 can be realized, whereby F is the minimum structural size of the respective technology.

    摘要翻译: PCT No.PCT / DE97 / 02549 Sec。 371 1999年6月21日第 102(e)日期1999年6月21日PCT 1997年11月4日PCT PCT。 第WO98 / 27586号公报 日期1998年6月25日为了制造具有包括垂直MOS晶体管的第一存储单元和不包括MOS晶体管的第二存储单元的存储单元布置,由此存储单元沿带状沟槽的相对边缘布置 沿着沟槽(5)相邻的存储单元依次制造。 特别是通过间隔物技术来确定相邻存储单元的间隔。 通过这种方式,可以实现1F2的每个存储单元的空间要求,由此F是相应技术的最小结构尺寸。

    Integrated circuit configuration and method for manufacturing it
    9.
    发明授权
    Integrated circuit configuration and method for manufacturing it 有权
    集成电路配置及其制造方法

    公开(公告)号:US06576948B2

    公开(公告)日:2003-06-10

    申请号:US09873231

    申请日:2001-06-04

    IPC分类号: H01L27108

    CPC分类号: H01L27/108

    摘要: An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.

    摘要翻译: 集成电路包含平面第一晶体管和二极管。 二极管连接在第一晶体管的第一源极/漏极区域和第一晶体管的栅电极之间,使得电荷被阻止从栅电极放电到第一源极/漏极区域。 作为二极管的一部分的二极管层设置在第一源极/漏极区域的一部分上。 作为二极管的附加部分的导电结构设置在栅电极的一部分上方并且设置在二极管层上。 二极管可以配置为隧道二极管。 二极管层可以通过热氧化生产。 制造二极管只需要一个掩模。 电容器可以设置在二极管的上方。 电容器的第一电容器电极连接到导电结构。

    Method for production of a memory cell arrangement
    10.
    发明授权
    Method for production of a memory cell arrangement 失效
    存储单元布置的制造方法

    公开(公告)号:US06475866B2

    公开(公告)日:2002-11-05

    申请号:US09774316

    申请日:2001-01-31

    IPC分类号: H01L21336

    摘要: A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).

    摘要翻译: 一种用于生产包括垂直MOS晶体管作为存储单元的存储单元布置的方法,其中通过多级编程利用晶体管的至少三个不同阈值电压值存储信息。 通过厚氧化物晶体管的意义上的栅极电介质的厚度实现一个阈值电压值,并且通过不同的沟道掺杂实现其它阈值电压值。 可以按照2 F2(F:最小结构尺寸)的每个存储单元的面积要求来生成该布置。