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113 条记录 (耗时 0.021 秒)

    Semiconductor device
    21.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06914300B2

    公开(公告)日：2005-07-05

    申请号：US10653198

    申请日：2003-09-03

    申请人： Masakazu Hirose ,  Fukashi Morishita

    发明人： Masakazu Hirose ,  Fukashi Morishita

    IPC分类号： H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/52 ,  H01L27/01 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H01L31/0392

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： In a potential interconnection layer, when viewed from a plane, a plurality of power supply potential regions and ground potential regions are alternately provided, with an interlayer insulation layer lying therebetween. A contact plug penetrating a second insulation layer is provided to electrically connect a source/drain (S/D) region on one side of a selected field effect transistor with a selected power supply potential region. Similarly, a contact plug penetrating the second insulation layer is provided to electrically connect a source/drain (S/D) region on the other side of another selected field effect transistor with a selected ground potential region. By employing this structure, a semiconductor device having a plurality of semiconductor circuits in which a power supply potential and a ground potential can be stabilized regardless of the cross-sectional structure of the semiconductor device is provided.

    摘要翻译： 在潜在的互连层中，当从平面观察时，交替地设置多个电源电位区域和接地电位区域，层间绝缘层位于其间。 提供穿透第二绝缘层的接触插塞以将选定的场效应晶体管的一侧上的源极/漏极（S / D）区域与选定的电源电位区域电连接。 类似地，穿过第二绝缘层的接触插塞被提供以将另一个选择的场效应晶体管的另一侧上的源极/漏极（S / D）区域与选择的接地电位区域电连接。 通过采用这种结构，提供了具有能够稳定电源电位和接地电位的多个半导体电路的半导体器件，而与半导体器件的横截面结构无关。

    Clock generating circuit
    22.
    发明授权
    Clock generating circuit 失效
    时钟发生电路

    公开(公告)号：US06781431B2

    公开(公告)日：2004-08-24

    申请号：US10349033

    申请日：2003-01-23

    申请人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

    发明人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

    IPC分类号： G06F104

    CPC分类号： H03K3/0315 ,  H02M3/07 ,  H03K3/013 ,  H03K3/70

    摘要： The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.

    摘要翻译： 用于产生时钟信号的时钟发生电路包括具有以环形配置连接的奇数个反相器的环形振荡器。 当激活信号处于第一电平时，环形振荡器被激活以产生时钟信号，并且当激活信号处于第二电平时被停止产生时钟信号。 锁存电路连接到环形振荡器的输出节点，并且响应于激活信号从第一电平到第二电平的转变而保持环形振荡器的输出节点的电平。 当激活信号从H电平降低到L电平时，锁存时钟信号的电平，从而防止产生时钟信号中的毛刺。

    Semiconductor device reduced in through current
    24.
    发明授权
    Semiconductor device reduced in through current 失效
    半导体器件通过电流减小

    公开(公告)号：US06483357B2

    公开(公告)日：2002-11-19

    申请号：US09811578

    申请日：2001-03-20

    申请人： Hiroshi Kato ,  Fukashi Morishita

    发明人： Hiroshi Kato ,  Fukashi Morishita

    IPC分类号： H03L700

    CPC分类号： G05F1/465

    摘要： A sense signal IVOFF is generated by a power supply level sense circuit with an external power supply potential Ext.Vcc1 as the operating power supply potential to sense the level of an external power supply potential Ext.Vcc2. By suppressing generation of an internal power supply potential or fixing the internal node by the sense signal IVOFF, the through current at the time of power on can be reduced.

    摘要翻译： 感测信号IVOFF由电源电平检测电路产生，外部电源电位Ext.Vcc1作为工作电源电位，用于感测外部电源电位Ext.Vcc2的电平。 通过抑制内部电源电位的产生或通过感测信号IVOFF固定内部节点，可以减少上电时的通过电流。

    Boosting circuit compensating for voltage fluctuation due to operation of load
    26.
    发明授权
    Boosting circuit compensating for voltage fluctuation due to operation of load 失效
    升压电路补偿由于负载操作引起的电压波动

    公开(公告)号：US6154411A

    公开(公告)日：2000-11-28

    申请号：US324802

    申请日：1999-06-03

    申请人： Fukashi Morishita

    发明人： Fukashi Morishita

    IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  H02M3/07 ,  G11C7/00

    CPC分类号： G11C5/145 ,  G11C11/4074

    摘要： A boosting circuit is provided with a voltage detection circuit, first through fourth oscillators, and first through fourth charge pump circuits. The voltage detection circuit compares each of the first through fourth voltages obtained by dividing a boosted voltage with a reference voltage, and generates first through fourth activation signals. The first through fourth oscillators output pulse signals at first through fourth frequencies, respectively, as first through fourth drive signals. The first through fourth charge pump circuits operate in response to the first through fourth drive signals, respectively, and boost the boosted voltage. Accordingly, it is possible to provide a stable boosted voltage, with suppressing over shoot and under shoot with respect to the boosted voltage as a target.

    摘要翻译： 升压电路具有电压检测电路，第一至第四振荡器以及第一至第四电荷泵电路。 电压检测电路将通过将升压电压分压获得的第一至第四电压与参考电压进行比较，并且产生第一至第四激活信号。 第一至第四振荡器分别以第一至第四驱动信号在第一至第四频率处输出脉冲信号。 第一至第四电荷泵电路分别响应于第一至第四驱动信号而工作，并升压升压电压。 因此，可以提供稳定的升压电压，相对于作为目标的升压电压抑制过拍和下拍。

    Semiconductor integrated circuit device having stable input protection circuit
    27.
    发明授权
    Semiconductor integrated circuit device having stable input protection circuit 失效
    半导体集成电路器件具有稳定的输入保护电路

    公开(公告)号：US5909046A

    公开(公告)日：1999-06-01

    申请号：US965618

    申请日：1997-11-06

    申请人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

    发明人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L23/62

    CPC分类号： H01L27/0248 ,  H01L24/05 ,  H01L2924/14

    摘要： A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.

    摘要翻译： 导体线被放置在覆盖输入保护电路的层上，该输入保护电路电耦合到焊盘，使得导线覆盖输入保护电路的至少一部分。 具有足够大的宽度的导体线分散并吸收从输入保护电路产生的热量。 由于输入保护电路和导体线在平面图的布局中具有彼此重叠的区域，因此可以有效地降低芯片上的输入保护电路布局的区域，并防止保护电路的破坏 可以获得耐热性，并且可以获得耐喘振性的改善。

    Semiconductor device
    28.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08466718B2

    公开(公告)日：2013-06-18

    申请号：US13081957

    申请日：2011-04-07

    申请人： Yoshiyuki Ezumi ,  Fukashi Morishita

    发明人： Yoshiyuki Ezumi ,  Fukashi Morishita

    IPC分类号： H03K3/00

    CPC分类号： H03K19/00361 ,  H03K19/018528

    摘要： Disclosed is a semiconductor device having an output driver and a driver replica. The output driver is based on a scalable low-voltage signaling technology and capable of operating on low power and making automatic adjustments of output characteristics in accordance with the magnitude of a reference current. The driver replica, which is a duplicate of the output driver, adjusts the magnitude of the reference current in accordance with the difference between its own output and a reference voltage and outputs the adjusted current to the output driver.

    摘要翻译： 公开了具有输出驱动器和驱动器副本的半导体器件。 输出驱动器基于可扩展的低电压信号技术，能够以低功耗运行，并根据参考电流的大小自动调整输出特性。 与输出驱动器重复的驱动器副本根据其自身的输出和参考电压之间的差异来调整参考电流的大小，并将调整的电流输出到输出驱动器。

    Semiconductor device including internal voltage generation circuit
    29.
    发明授权
    Semiconductor device including internal voltage generation circuit 失效
    半导体器件包括内部电压产生电路

    公开(公告)号：US08451678B2

    公开(公告)日：2013-05-28

    申请号：US13080114

    申请日：2011-04-05

    申请人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

    发明人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

    IPC分类号： G11C5/14

    CPC分类号： G05F1/468 ,  G11C5/025 ,  G11C5/147

    摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

    摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

    Semiconductor memory device
    30.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08188534B2

    公开(公告)日：2012-05-29

    申请号：US13022864

    申请日：2011-02-08

    申请人： Fukashi Morishita ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Kazutami Arimoto

    IPC分类号： H01L29/788 ,  H01L27/01 ,  H01L27/12

    CPC分类号： G11C11/405 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

    摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

    摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。