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    Semiconductor integrated circuit device having stable input protection circuit
    1.
    发明授权
    Semiconductor integrated circuit device having stable input protection circuit 失效
    半导体集成电路器件具有稳定的输入保护电路

    公开(公告)号：US5909046A

    公开(公告)日：1999-06-01

    申请号：US965618

    申请日：1997-11-06

    申请人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

    发明人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L23/62

    CPC分类号： H01L27/0248 ,  H01L24/05 ,  H01L2924/14

    摘要： A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.

    摘要翻译： 导体线被放置在覆盖输入保护电路的层上，该输入保护电路电耦合到焊盘，使得导线覆盖输入保护电路的至少一部分。 具有足够大的宽度的导体线分散并吸收从输入保护电路产生的热量。 由于输入保护电路和导体线在平面图的布局中具有彼此重叠的区域，因此可以有效地降低芯片上的输入保护电路布局的区域，并防止保护电路的破坏 可以获得耐热性，并且可以获得耐喘振性的改善。

    Semiconductor integrated circuit device having a test mode for reliability evaluation
    2.
    发明授权
    Semiconductor integrated circuit device having a test mode for reliability evaluation 失效
    具有用于可靠性评估的测试模式的半导体集成电路器件

    公开(公告)号：US5694364A

    公开(公告)日：1997-12-02

    申请号：US779186

    申请日：1997-01-06

    申请人： Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

    IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C29/00 ,  G11C29/06 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

    CPC分类号： G11C5/147

    摘要： In the normal mode, a first voltage-down converter down-converts an external power supply voltage to provide a large, first internal power supply voltage to the peripheral circuitry via a first internal power supply voltage supplying line, and a second voltage-down converter down-converts the external power supply voltage to provide a smaller, second internal power supply voltage to a memory cell array via a second internal power supply voltage supplying line. This allows fast operation and reduction in power consumption. In conducting a burn-in test, an external power supply voltage supplying line is connected to the first and second internal power supply voltage supplying lines. Thus, the first and second internal power supply voltage supplying lines directly receive the external power supply voltage. This allows an effective burn-in test. In a burn-in test, the first and second voltage-down converters are inactivated.

    摘要翻译： 在正常模式中，第一降压转换器对外部电源电压进行下变频，以经由第一内部电源电压供应线向外围电路提供大的第一内部电源电压，以及第二降压转换器 降低外部电源电压，以经由第二内部电源电压供给线向存储单元阵列提供较小的第二内部电源电压。 这允许快速操作和降低功耗。 在进行老化试验时，外部电源电压供给线与第一和第二内部电源电压供给线连接。 因此，第一和第二内部电源电压供给线直接接收外部电源电压。 这允许有效的老化测试。 在老化测试中，第一和第二降压转换器失效。

    Semiconductor integrated circuit device having hierarchical power source arrangement
    3.
    发明授权
    Semiconductor integrated circuit device having hierarchical power source arrangement 有权
    具有分层电源布置的半导体集成电路器件

    公开(公告)号：US06341098B2

    公开(公告)日：2002-01-22

    申请号：US09846223

    申请日：2001-05-02

    申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

    发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

    IPC分类号： G11C700

    CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

    摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

    摘要翻译： 分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在 列电路有效时间段。 可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。 根据待机周期和激活周期中的输出信号的逻辑电平，变频器作为电压VCL1和VSL2的工作电源电压或电压VCL2和VSL1运行。 因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。

    Switched substrate bias for MOS DRAM circuits
    5.
    发明授权
    Switched substrate bias for MOS DRAM circuits 失效
    用于MOS DRAM电路的开关衬底偏置

    公开(公告)号：US5854561A

    公开(公告)日：1998-12-29

    申请号：US957426

    申请日：1997-10-24

    申请人： Kazutami Arimoto ,  Masaki Tsukude

    发明人： Kazutami Arimoto ,  Masaki Tsukude

    IPC分类号： H01L27/02 ,  H01L27/12 ,  H03K19/00 ,  G05F3/16 ,  H03K17/16

    CPC分类号： H01L27/1203 ,  H01L27/0218 ,  H03K19/0016 ,  H03K2217/0018

    摘要： A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

    摘要翻译： 一种半导体电路或MOS-DRAM，其中提供了转换装置，其将MOS-FET的逻辑电路，存储单元和工作电路中的MOS-FET的两个值之间的衬底电位或体偏置电位转换，从而提高阈值电压 的MOS-FET在处于待机状态时，并且在处于活动状态时将其降低。 转换装置包括电平移位电路和开关电路。 衬底电位或体偏置电位仅受待机状态下不导通的MOS-FET的控制; 该配置实现了与潜在切换相关联的功耗的降低。 此外，在相邻形成相同导电类型的MOS-FET的结构中，为了更好的结果，优选SOI结构的MOS-FET。

    Arrangement of power supply and data input/output pads in semiconductor memory device
    6.
    发明授权
    Arrangement of power supply and data input/output pads in semiconductor memory device 失效
    半导体存储器件中电源和数据输入/输出焊盘的布置

    公开(公告)号：US5838627A

    公开(公告)日：1998-11-17

    申请号：US768090

    申请日：1996-12-16

    申请人： Shigeki Tomishima ,  Mikio Asakura ,  Masaki Tsukude ,  Kazutami Arimoto

    发明人： Shigeki Tomishima ,  Mikio Asakura ,  Masaki Tsukude ,  Kazutami Arimoto

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  G11C29/26 ,  G11C29/34 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C5/14 ,  G11C29/26 ,  G11C29/34 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10

    摘要： Data input/output pad portions are arranged corresponding to memory blocks and adjacent to a corresponding memory block in the center region between memory blocks, and memory blocks. Power supply pads are arranged at both ends of the center region. Power supply pad transmits a power supply voltage to data input/output pad portions, and power supply pad transmits the power supply voltage to data input/output pad portions. Power supply pad for peripheral circuitry is arranged in the center portion of the center region. A multibit test circuit is provided for each memory block. A data input/output buffer operating stably at high speed is implemented in a large storage capacity memory device which in turn accommodates a multibit test mode.

    摘要翻译： 数据输入/输出焊盘部分对应于存储块并且与存储块和存储块之间的中心区域中相应的存储块相邻布置。 电源垫布置在中心区域的两端。 电源板将电源电压发送到数据输入/输出焊盘部分，电源焊盘将电源电压发送到数据输入/输出焊盘部分。 用于外围电路的电源板布置在中心区域的中心部分。 为每个存储块提供多位测试电路。 在大容量存储装置中实现高速稳定运行的数据输入/输出缓冲器，其又适应多位测试模式。

    Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device
    7.
    发明授权
    Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device 失效
    感测放大器包括具有在半导体存储器件中动态控制的阈值电压的MOS晶体管

    公开(公告)号：US5646900A

    公开(公告)日：1997-07-08

    申请号：US583893

    申请日：1996-01-11

    申请人： Masaki Tsukude ,  Kazutami Arimoto

    发明人： Masaki Tsukude ,  Kazutami Arimoto

    IPC分类号： G11C11/409 ,  G11C5/14 ,  G11C7/06 ,  G11C11/407 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/419

    CPC分类号： G11C7/065 ,  G11C5/146

    摘要： N channel sense amplifier transistors have their backgate potentials set to a backgate precharge potential higher than a potential intermediate between an operation power supply potential and a ground potential prior to start of sensing operation, and then lowered following the lowering of an n common source node potential during the sensing operation. The n common source node is precharged to the intermediate potential. The backgate precharge potential is set no greater than a potential of the intermediate potential plus a pn junction diffusion, to suppress a leakage current from the backgate to source or drain of each of the sense amplifier transistors. P channel sense amplifier transistors have also their backgate potential set to a precharge potential lower than the intermediate potential prior to sensing operation and raised following the rise of a p common source node potential.

    摘要翻译： N沟道读出放大器晶体管的背栅电位被设置为比开始感测操作之前的工作电源电位和地电位之间的电位中间高的后栅极预充电电位，然后在n个共同源节点电位降低之后降低 在感测操作期间。 n个公共源节点被预充电到中间电位。 背栅预充电电位被设定为不大于中间电位加上pn结扩散的电位，以抑制从每个读出放大器晶体管的背栅到源极或漏极的漏电流。 P沟道读出放大器晶体管在其感测操作之前也将其背栅电位设置为低于中间电位的预充电电位，并且随着p共同源节点电位的上升而升高。

    Switched substrate bias for logic circuits
    8.
    发明授权
    Switched substrate bias for logic circuits 失效
    用于逻辑电路的开关衬底偏置

    公开(公告)号：US5610533A

    公开(公告)日：1997-03-11

    申请号：US350064

    申请日：1994-11-29

    申请人： Kazutami Arimoto ,  Masaki Tsukude

    发明人： Kazutami Arimoto ,  Masaki Tsukude

    IPC分类号： H01L27/02 ,  H01L27/12 ,  H03K19/00 ,  H03K17/16

    CPC分类号： H01L27/1203 ,  H01L27/0218 ,  H03K19/0016 ,  H03K2217/0018

    摘要： A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

    摘要翻译： 一种半导体电路或MOS-DRAM，其中提供了转换装置，其将MOS-FET的逻辑电路，存储单元和工作电路中的MOS-FET的两个值之间的衬底电位或体偏置电位转换，从而提高阈值电压 的MOS-FET在处于待机状态时，并且在处于活动状态时将其降低。 转换装置包括电平移位电路和开关电路。 衬底电位或体偏置电位仅受待机状态下不导通的MOS-FET的控制; 该配置实现了与潜在切换相关联的功耗的降低。 此外，在相邻形成相同导电类型的MOS-FET的结构中，为了更好的结果，优选SOI结构的MOS-FET。