公开(公告)号：US09627508B2

公开(公告)日：2017-04-18

申请号：US14685944

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/88 ,  H01L29/20 ,  H01L21/02 ,  H01L29/739 ,  H01L29/267

CPC classification number: H01L29/66545 ,  H01L21/02538 ,  H01L21/02617 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66151 ,  H01L29/66356 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/88

Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.

公开(公告)号：US20170047255A1

公开(公告)日：2017-02-16

申请号：US15338894

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Min Dai ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L21/8234 ,  H01L21/324 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

Abstract: Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

Abstract translation: 硅 - 锗表面层在半导体表面上的选择性沉积可用于为场效应晶体管提供两种类型的沟道区。 在硅基栅极电介质和高介电常数（高k）栅极电介质的堆叠上的调整氧化物材料的退火可以用于形成接触通道区域子集的界面调整氧化物层。 通过沉积第一功函数金属材料层和封盖层和随后的退火，可以在覆盖界面调整氧化物层的高k电介质层的部分中诱导氧缺乏。 可以通过物理暴露高k电介质层的部分来选择性地去除氧缺乏。 可以将第二功函数金属材料层和栅极导体层沉积并平坦化以形成提供多个有效功函数的栅电极。

公开(公告)号：US09548381B1

公开(公告)日：2017-01-17

申请号：US14967946

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/45 ,  H01L29/267 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/0673 ,  H01L29/267 ,  H01L29/66356 ,  H01L29/66742 ,  H01L29/7391 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/78696

Abstract: A heterojunction tunnel field effect transistor (TFET) has a channel region that includes a first portion of a nanowire, a source region and a drain region that respectively include a second portion and a third portion of a nanowire, and a gate that surrounds the channel region, where the first portion of the nanowire comprises an intrinsic, epitaxial III-V semiconductor. The TFET can be made by selectively etching the epitaxial underlayer to define a tethered (suspended) nanowire that forms a channel region of the device. Source and drain regions can be formed from regrown p-type and n-type epitaxial layers.

Abstract translation: 异质结隧道场效应晶体管（TFET）具有沟道区，该沟道区包括分别包括纳米线的第二部分和第三部分的纳米线的第一部分，源极区和漏极区，以及包围沟道的栅极 区域，其中纳米线的第一部分包括本征的外延III-V半导体。 可以通过选择性地蚀刻外延底层来形成TFET，以限定形成该器件的沟道区的系留（悬挂）的纳米线。 源极和漏极区可以由再生长的p型和n型外延层形成。

公开(公告)号：US20160086849A1

公开(公告)日：2016-03-24

申请号：US14490792

申请日：2014-09-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Joyeeta Nag ,  Andrew H. Simon ,  Shishir Ray

IPC: H01L21/768

CPC classification number: H01L21/76894 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/00

Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

Abstract translation: 密封铜线的原位熔融和结晶可以通过激光退火进行纳秒的持续时间。 选择激光照射的强度，使得熔融铜浸润互连界面，从而形成增加电子的镜面散射的界面结合装置。 纳秒级温度淬火保持形成的界面结合。 同时，密封铜互连的快速结晶过程平均导致大的铜晶粒，通常大于80nm的横向尺寸。 退火过程的典型持续时间为约10秒至约100秒的纳秒。 尽管由于超短时间的高退火温度，层间低k介电材料没有劣化，从而防止原子在电介质材料内的集体运动。

公开(公告)号：US09059315B2

公开(公告)日：2015-06-16

申请号：US13732455

申请日：2013-01-02

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, Jr. ,  Yanfeng Wang ,  Jinping Liu

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

CPC classification number: H01L21/823857

Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域之上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。