公开(公告)号：US10818557B2

公开(公告)日：2020-10-27

申请号：US16026130

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Akshey Sehgal ,  Xinyuan Dou ,  Sunil K. Singh ,  Ravi P. Srivastava ,  Haiting Wang ,  Scott H. Beasor

IPC: H01L21/8234 ,  H01L29/423 ,  H01L23/48 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

公开(公告)号：US10741495B2

公开(公告)日：2020-08-11

申请号：US15873946

申请日：2018-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Vinit O. Todi ,  Shao Beng Law

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

Abstract: In an exemplary method, a first dielectric layer is formed on a substrate. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is a carbon rich film and different from the first dielectric layer. A trench is formed through the first and second dielectric layers. A conductive line is formed in the trench. A third dielectric layer is formed on the second dielectric layer and conductive line. The material of the third dielectric layer is different from the second dielectric layer. A via opening is formed through the third dielectric layer and stops at the second dielectric layer with a portion of the conductive line exposed to the via opening. At the bottom of the via opening, a recess is formed in the second dielectric layer adjacent to the conductive line. The via opening and recess are filled with a conductive material contacting the conductive line.

公开(公告)号：US20200020531A1

公开(公告)日：2020-01-16

申请号：US16033714

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuping Ren ,  Guoxiang Ning ,  Haigou Huang ,  Sunil K. Singh

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.

公开(公告)号：US20190221523A1

公开(公告)日：2019-07-18

申请号：US15873946

申请日：2018-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Vinit O. Todi ,  Shao Beng Law

IPC: H01L23/532 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

Abstract: In an exemplary method, a first dielectric layer is formed on a substrate. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is a carbon rich film and different from the first dielectric layer. A trench is formed through the first and second dielectric layers. A conductive line is formed in the trench. A third dielectric layer is formed on the second dielectric layer and conductive line. The material of the third dielectric layer is different from the second dielectric layer. A via opening is formed through the third dielectric layer and stops at the second dielectric layer with a portion of the conductive line exposed to the via opening. At the bottom of the via opening, a recess is formed in the second dielectric layer adjacent to the conductive line. The via opening and recess are filled with a conductive material contacting the conductive line.

公开(公告)号：US10347528B1

公开(公告)日：2019-07-09

申请号：US15912975

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Sipeng Gu ,  Akshey Sehgal

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.

公开(公告)号：US10109706B1

公开(公告)日：2018-10-23

申请号：US15643721

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Devender ,  Sunil K. Singh ,  M. Golam Faruk ,  Dewei Xu

IPC: H01L21/31 ,  H01L49/02 ,  H01L21/311 ,  H01L21/027 ,  H01L21/283 ,  H01L21/3105 ,  H01L27/12

Abstract: The present disclosure describes a method or forming vertical natural capacitor (VNCAP) and the resulting device. The method includes applying a patterned mask over an insulation layer. The method includes forming using the patterned mask, a dielectric trench in the insulation layer. The method includes depositing a high dielectric constant k (high k) layer in the dielectric trench. The method includes forming a first trench and a second trench in the high k dielectric layer. The high k dielectric layer is disposed between the first trench and the second trench. The method includes depositing metal in the first trench and the second trench.

公开(公告)号：US20180204929A1

公开(公告)日：2018-07-19

申请号：US15407407

申请日：2017-01-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shiv K. Mishra ,  Sunil K. Singh

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/283 ,  H01L21/768 ,  H01L21/324 ,  H01L21/762 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods for forming a field-effect transistor. An interlayer dielectric layer is formed on a substrate. An energy removal film is formed on the interlayer dielectric layer, and at least one metal gate layer is formed on the energy removal film. After the at least one metal gate layer is polished, the energy removal film is removed from the interlayer dielectric layer. The removal of the energy removal film may remove metal residues generated by the polishing of the at least one metal gate layer so that the top surface of the interlayer dielectric layer is not contaminated by the metal residues.