公开(公告)号：US09171934B2

公开(公告)日：2015-10-27

申请号：US14242329

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, Jr. ,  Ryan Ryoung-Han Kim

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L21/02 ,  H01L21/265 ,  H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed includes, among other things, forming a plurality of laterally spaced-apart source/drain trenches and a gate trench in a layer of material above an active region, performing at least one process operation through the spaced-apart source/drain trenches to form doped source/drain regions, forming a gate structure within the gate trench, and forming a gate cap layer above the gate structure positioned within the gate trench.

Abstract translation: 所公开的一种方法包括在有源区上方的材料层中形成多个横向间隔开的源极/漏极沟槽和栅极沟槽，通过间隔开的源极/漏极沟槽进行至少一个工艺操作 以形成掺杂源极/漏极区域，在栅极沟槽内形成栅极结构，以及在位于栅极沟槽内的栅极结构上方形成栅极覆盖层。

公开(公告)号：US09117930B2

公开(公告)日：2015-08-25

申请号：US13960200

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。