公开(公告)号：US20140120677A1

公开(公告)日：2014-05-01

申请号：US13663854

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel T. Pham ,  Robert J. Miller ,  Kungsuk Maitra

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L21/26506 ,  H01L29/66795 ,  H01L29/7842

Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.

Abstract translation: 本文公开了通过使用外延形成的材料在3D半导体器件（例如FinFET半导体器件）上形成应力沟道区的各种方法。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定器件的鳍片的至少一部分，以及执行外延沉积工艺以形成外延形成的应力诱导材料 在壕沟里

公开(公告)号：US08889500B1

公开(公告)日：2014-11-18

申请号：US13960244

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

IPC: H01L21/338 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of fin-formation trenches that define a fin, forming a first stressed layer within the trenches and above the fin and performing at least one etching process on the first stressed layer so as to define spaced-apart portions of the first stressed layer positioned at least partially within the trenches on opposite sides of the fin. The method also includes forming spaced-apart portions of a second stressed layer above the spaced-apart portions of the first layer, forming a third stressed layer above the fin between the spaced-apart portions of the second layer and, after forming the third layer, forming a conductive layer above the second and third layers.

Abstract translation: 本文公开的一种说明性方法包括形成限定翅片的多个翅片形成沟槽，在沟槽内和翅片上方形成第一应力层，并在第一应力层上执行至少一个蚀刻工艺，以便 以限定至少部分地位于鳍片的相对侧上的沟槽内的第一应力层的间隔开的部分。 该方法还包括在第一层的间隔开的部分上方形成第二应力层的间隔开的部分，在第二层间隔开的部分之间形成翅片之上的第三应力层，在形成第三层之后 在第二层和第三层上形成导电层。

公开(公告)号：US09263585B2

公开(公告)日：2016-02-16

申请号：US13663854

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel T. Pham ,  Robert J. Miller ,  Kungsuk Maitra

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7851 ,  H01L21/26506 ,  H01L29/66795 ,  H01L29/7842

Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.

Abstract translation: 本文公开了通过使用外延形成的材料在3D半导体器件（例如FinFET半导体器件）上形成应力沟道区的各种方法。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定器件的鳍片的至少一部分，以及执行外延沉积工艺以形成外延形成的应力诱导材料 在壕沟里

公开(公告)号：US20150041906A1

公开(公告)日：2015-02-12

申请号：US13960200

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, JR.

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。

公开(公告)号：US20140191319A1

公开(公告)日：2014-07-10

申请号：US13733943

申请日：2013-01-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Kangguo Cheng ,  Shom Ponoth ,  Balasubramanian Pranatharthiharan ,  Theodorus Eduardus Standaert ,  Tenko Yamashita ,  Robert J. Miller

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L21/845 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/1211 ,  H01L29/861

Abstract: A diode for integration with finFET devices is disclosed. An in-situ doped epitaxial silicon region is grown on the cathode or anode of the diode to increase the surface area of the junction and overall silicon volume for improved heat dissipation during an ESD event.

Abstract translation: 公开了一种用于与finFET器件集成的二极管。 在二极管的阴极或阳极上生长原位掺杂的外延硅区域，以增加结的表面面积和整体硅体积，以改善ESD事件期间的散热。

公开(公告)号：US09117930B2

公开(公告)日：2015-08-25

申请号：US13960200

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。