公开(公告)号：US11309319B2

公开(公告)日：2022-04-19

申请号：US16984468

申请日：2020-08-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092

Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

公开(公告)号：US11217533B2

公开(公告)日：2022-01-04

申请号：US16784256

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Steven Robert Soss ,  Steven John Bentley ,  Julien Frougier

IPC: H01L23/522 ,  H01L29/78 ,  H01L23/535 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures.

公开(公告)号：US11164867B2

公开(公告)日：2021-11-02

申请号：US16534361

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Julien Frougier ,  Ruilong Xie ,  Anthony K. Stamper

IPC: H01L29/04 ,  H01L29/786 ,  H01L27/088 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/324

Abstract: Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.

公开(公告)号：US11158574B2

公开(公告)日：2021-10-26

申请号：US16726497

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/528 ,  H01L45/00 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L23/522

Abstract: One illustrative device disclosed herein includes a layer of insulating material with its upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein a recessed upper surface of the recessed conductive interconnect structure is positioned at a second level that is below the first level. In this example, the device also includes a conductive cap layer positioned on the recessed upper surface of the recessed conductive interconnect structure, wherein an upper surface of the conductive cap layer is substantially co-planar with the upper surface of the layer of insulating material and a memory cell positioned above the conductive cap layer, wherein the memory cell comprises a lower conductive material that is conductively coupled to the conductive cap layer.

公开(公告)号：US11094794B2

公开(公告)日：2021-08-17

申请号：US16585671

申请日：2019-09-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Julien Frougier ,  Ali Razavieh ,  Haiting Wang

IPC: H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L21/764 ,  H01L21/768 ,  H01L21/306

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to air spacer structures and methods of manufacture. The structure includes: a plurality of gate structures comprising active regions; contacts extending to the active regions; a plurality of anchor structures between the active regions; and air spacer structures adjacent to the contacts.

公开(公告)号：US20210233999A1

公开(公告)日：2021-07-29

申请号：US16774157

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Ali Razavieh ,  Julien Frougier

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06

Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.