公开(公告)号：US20070161170A1

公开(公告)日：2007-07-12

申请号：US11311587

申请日：2005-12-16

申请人： Marius Orlowski ,  James Burnett

发明人： Marius Orlowski ,  James Burnett

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/41791 ,  H01L29/785 ,  H01L2029/7858

摘要： A method includes forming a semiconductor structure, the semiconductor structure includes a first current electrode region, a second current electrode region, and a channel region, the channel region is located between the first current electrode region and the second current electrode region, wherein the channel region is located in a fin structure of the semiconductor structure, wherein a carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. The method further includes forming a first contact, wherein forming the first contact includes removing a first portion of the semiconductor structure to form an opening, wherein the opening is in the first current electrode region and forming contact material in the opening.

摘要翻译： 一种包括形成半导体结构的方法，所述半导体结构包括第一电流电极区域，第二电流电极区域和沟道区域，所述沟道区域位于所述第一电流电极区域和所述第二电流电极区域之间，其中所述沟道 区域位于半导体结构的翅片结构中，其中通道区域中的载流子传输通常在第一电流电极区域和第二电流电极区域之间的水平方向上。 所述方法还包括形成第一接触，其中形成所述第一接触包括移除所述半导体结构的第一部分以形成开口，其中所述开口位于所述第一电流电极区域中并在所述开口中形成接触材料。

公开(公告)号：US20070158730A1

公开(公告)日：2007-07-12

申请号：US11328779

申请日：2006-01-10

申请人： James Burnett ,  Leo Mathew ,  Byoung Min

发明人： James Burnett ,  Leo Mathew ,  Byoung Min

IPC分类号： H01L29/76

CPC分类号： H01L27/1108 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).

摘要翻译： 集成电路包括逻辑电路和存储单元。 逻辑电路包括P沟道晶体管，并且存储单元包括P沟道晶体管。 逻辑电路的P沟道晶体管包括沟道区。 沟道区具有位于具有（110）表面取向的半导体结构的侧壁的部分。 位于沿着侧壁的通道区域的部分具有第一垂直尺寸，其大于沿着具有表面的半导体结构的侧壁的存储单元的P沟道晶体管的沟道区的任何部分的垂直尺寸 （110）的方向。

公开(公告)号：US20070001222A1

公开(公告)日：2007-01-04

申请号：US11172569

申请日：2005-06-30

申请人： Marius Orlowski ,  James Burnett

发明人： Marius Orlowski ,  James Burnett

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/7841 ,  H01L29/78687

摘要： A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.

摘要翻译： 半导体制造方法包括形成半导体结构，该半导体结构包括设置在沟道体两侧的源极/漏极区，其中源极/漏极区包括第一半导体材料，并且其中沟道主体包括第二半导体材料的迁移势垒。 栅极电介质覆盖半导体结构，并且栅极模块覆盖在栅极电介质上。 在第一和第二半导体材料之间的多数载流子势能级中的偏移对于通道体中的多数载流子产生潜在的井。 迁移障碍物可以是第一半导体材料的第一层上的第二半导体材料层和第一半导体材料的覆盖层之下的层。 在一维迁移屏障中，迁移屏障横向延伸穿过源极/漏极区域，而在二维屏障中，屏障在由栅极模块限定的边界处横向终止。

公开(公告)号：US20060068542A1

公开(公告)日：2006-03-30

申请号：US10955658

申请日：2004-09-30

申请人： Marius Orlowski ,  James Burnett

发明人： Marius Orlowski ,  James Burnett

IPC分类号： H01L21/8238

CPC分类号： H01L21/823878 ,  H01L21/76237

摘要： A method of forming isolation trenches in a semiconductor fabrication process to reduce transistor channel edge effect currents includes forming a masking structure overlying a substrate to expose a first area of the substrate. Spacers are formed on sidewalls of the masking structure. The spacers cover a perimeter region of the first area thereby leaving a second smaller area exposed. The region underlying the second area is etched to form an isolation trench that is then filled with a dielectric. The spacers are removed to expose the perimeter region. Using the masking structure and the trench dielectric as a mask, an impurity distribution is implanted into a portion of the substrate underlying the perimeter region. The impurity distribution thus surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate. The perimeter impurity distribution dopant, in a typical case, is p-type for NMOS transistors and n-type for PMOS.

摘要翻译： 在半导体制造工艺中形成隔离沟槽以减少晶体管沟道边缘效应电流的方法包括形成覆盖衬底的掩模结构以暴露衬底的第一区域。 隔板形成在掩蔽结构的侧壁上。 间隔物覆盖第一区域的周边区域，从而留下暴露的第二较小区域。 蚀刻第二区域下面的区域以形成隔离沟槽，然后填充电介质。 去除间隔物以露出周边区域。 使用掩模结构和沟槽电介质作为掩模，杂质分布被注入在周边区域下面的衬底的一部分中。 因此，杂质分布围绕靠近衬底的上表面的沟槽电介质的周边。 在典型情况下，周边杂质分布掺杂剂对于NMOS晶体管为p型，对于PMOS为n型。

公开(公告)号：US20050266643A1

公开(公告)日：2005-12-01

申请号：US10857545

申请日：2004-05-28

申请人： James Burnett ,  Suresh Venkatesan

发明人： James Burnett ,  Suresh Venkatesan

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A memory cell includes devices having associated isolation recesses of differing magnitudes. The effective channel width of a corresponding transistor is substantially equal to a channel top surface width plus twice a sidewall width formed by the isolation recesses. In an SRAM cell, a latch transistor has a larger effective channel width than an associated pass transistor by forming larger recesses, and therefore larger sidewalls in isolation layers surrounding the latch transistor and limiting such recesses for pass transistors. During manufacture of the memory cell, a mask is used to mask an area of the pass transistor while exposing an area of the latch transistor. Accordingly, recesses in an isolation layer around the latch transistor are formed without affecting a corresponding area around the pass transistor.

摘要翻译： 存储单元包括具有不同幅度的相关隔离凹槽的装置。 相应晶体管的有效沟道宽度基本上等于沟道顶表面宽度加上由隔离凹槽形成的两倍的侧壁宽度。 在SRAM单元中，通过形成较大的凹槽，因此锁存晶体管具有比关联的通过晶体管更大的有效沟道宽度，并且因此在围绕锁存晶体管的隔离层中较大的侧壁限制了用于传输晶体管的这种凹槽。 在存储单元的制造期间，使用掩模来掩蔽传输晶体管的区域，同时暴露锁存晶体管的区域。 因此，形成在锁存晶体管周围的隔离层中的凹槽，而不影响传输晶体管周围的相应区域。

公开(公告)号：US20080019206A1

公开(公告)日：2008-01-24

申请号：US11863961

申请日：2007-09-28

申请人： Prashant Kenkare ,  Andrew Russell ,  David Bearden ,  James Burnett ,  Troy Cooper ,  Shayan Zhang

发明人： Prashant Kenkare ,  Andrew Russell ,  David Bearden ,  James Burnett ,  Troy Cooper ,  Shayan Zhang

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/147 ,  G11C11/419

摘要： An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells. The integrated circuit may further include a second power supply voltage terminal for receiving a second power supply voltage higher than the first power supply voltage, wherein the second power supply voltage is provided to power the plurality of memory cells during a second access operation of the plurality of memory cells.

摘要翻译： 提供具有低电压读/写操作的集成电路。 集成电路可以包括处理器和以行和列组织并且耦合到处理器的多个存储单元，其中存储单元行包括字线和耦合到字线的所有存储器单元，并且其中列 的存储器单元包括位线和耦合到位线的所有存储器单元。 集成电路还可以包括用于接收第一电源电压的第一电源电压端子，其中提供第一电源电压以为处理器供电，并且其中提供第一电源电压以在多个存储器单元期间供电 多个存储单元的第一访问操作。 集成电路还可以包括用于接收高于第一电源电压的第二电源电压的第二电源电压端子，其中提供第二电源电压以在多个存储器单元的第二访问操作期间为多个存储器单元供电 的记忆细胞。

公开(公告)号：US20070218618A1

公开(公告)日：2007-09-20

申请号：US11754728

申请日：2007-05-29

申请人： James Burnett ,  Jon Cheek

发明人： James Burnett ,  Jon Cheek

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S257/903

摘要： An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

摘要翻译： 具有逻辑和静态随机存取存储器（SRAM）阵列的集成电路通过针对SRAM阵列处理不同于逻辑的层间电介质（ILD）而提高了性能。 N沟道逻辑和SRAM晶体管具有非压缩应力的ILD，P沟道逻辑晶体管ILD具有压缩应力，P沟道SRAM晶体管至少具有比P沟道逻辑晶体管更小的压缩应力，即P沟道SRAM 晶体管可以是压缩的，但是比P沟道逻辑晶体管更小，可以被放宽，或者可以是拉伸的。 P沟道SRAM晶体管的集成电路具有比P沟道逻辑晶体管更低的迁移率是有益的。 具有较低移动性的P沟道SRAM晶体管导致更好的写入性能; 在更低的电源电压下更好地写入时间或写入裕度。

公开(公告)号：US20070211517A1

公开(公告)日：2007-09-13

申请号：US11373584

申请日：2006-03-10

申请人： James Burnett

发明人： James Burnett

IPC分类号： G11C11/00 ,  G11C11/34

CPC分类号： G11C11/419

摘要： A first gate of a multi-gate transistor within a pass gate can be provided with a bias voltage to alter the bias point of the multi-gate transistor. The bias point can be controlled differently during different phases of memory cell operation and the bias point can provide operational improvements during each phase of memory cell operation. In a specific configuration the multi-gate semiconductor device has a first current electrode connected to a first node of a bit cell, a second current electrode connected to a bit line, and a second gate electrode connected to a read/write line, wherein the control module can alter the bias point of the multi-gate semiconductor differently during different phases of memory cell operation. In one embodiment a FinFET can be connected in a parallel configuration with the multi-gate transistor.

摘要翻译： 可以在通过栅极内的多栅极晶体管的第一栅极提供偏置电压以改变多栅极晶体管的偏置点。 可以在存储器单元操作的不同阶段期间不同地控制偏置点，并且偏置点可以在存储器单元操作的每个阶段期间提供操作改进。 在特定结构中，多栅极半导体器件具有连接到位单元的第一节点的第一电流电极，连接到位线的第二电流电极和连接到读取/写入线的第二栅电极，其中， 控制模块可以在存储器单元操作的不同阶段期间不同地改变多栅极半导体的偏置点。 在一个实施例中，FinFET可以与多栅极晶体管并联配置连接。

公开(公告)号：US20070161171A1

公开(公告)日：2007-07-12

申请号：US11328668

申请日：2006-01-10

申请人： James Burnett ,  Leo Mathew ,  Byoung Min

发明人： James Burnett ,  Leo Mathew ,  Byoung Min

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.

摘要翻译： 用于形成电子器件的工艺可以包括形成用于鳍型结构的第一高度的半导体鳍片，并且去除半导体鳍片的一部分，使得半导体鳍片缩短到第二高度。 根据具体实施例，可以形成第二半导体鳍片，第一和第二半导体鳍片中的每一个具有表示沟道宽度的不同高度。 根据另一具体实施例，可以形成第二和第三半导体鳍片，第一，第二和第三半导体鳍片中的每一个具有代表沟道宽度的不同高度。

公开(公告)号：US20070093043A1

公开(公告)日：2007-04-26

申请号：US11260849

申请日：2005-10-26

申请人： Brian Winstead ,  James Burnett ,  Sinan Goktepeli

发明人： Brian Winstead ,  James Burnett ,  Sinan Goktepeli

IPC分类号： H01L21/04

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device. The semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.

摘要翻译： 半导体结构包括具有存储区域和逻辑区域的衬底。 第一p型器件形成在存储器区域中，并且第二p型器件形成在逻辑区域中。 第一p型器件的半导体栅极的至少一部分具有比第二p型器件的半导体栅极的至少一部分更低的p型掺杂剂浓度。 第一和第二p型器件的半导体栅极各自具有非零p型掺杂剂浓度。