公开(公告)号：US20070218618A1

公开(公告)日：2007-09-20

申请号：US11754728

申请日：2007-05-29

申请人： James Burnett ,  Jon Cheek

发明人： James Burnett ,  Jon Cheek

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S257/903

摘要： An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

摘要翻译： 具有逻辑和静态随机存取存储器（SRAM）阵列的集成电路通过针对SRAM阵列处理不同于逻辑的层间电介质（ILD）而提高了性能。 N沟道逻辑和SRAM晶体管具有非压缩应力的ILD，P沟道逻辑晶体管ILD具有压缩应力，P沟道SRAM晶体管至少具有比P沟道逻辑晶体管更小的压缩应力，即P沟道SRAM 晶体管可以是压缩的，但是比P沟道逻辑晶体管更小，可以被放宽，或者可以是拉伸的。 P沟道SRAM晶体管的集成电路具有比P沟道逻辑晶体管更低的迁移率是有益的。 具有较低移动性的P沟道SRAM晶体管导致更好的写入性能; 在更低的电源电压下更好地写入时间或写入裕度。

公开(公告)号：US20060226490A1

公开(公告)日：2006-10-12

申请号：US11100168

申请日：2005-04-06

申请人： James Burnett ,  Jon Cheek

发明人： James Burnett ,  Jon Cheek

IPC分类号： H01L29/76

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S257/903

摘要： An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

摘要翻译： 具有逻辑和静态随机存取存储器（SRAM）阵列的集成电路通过针对SRAM阵列处理不同于逻辑的层间电介质（ILD）而提高了性能。 N沟道逻辑和SRAM晶体管具有非压缩应力的ILD，P沟道逻辑晶体管ILD具有压缩应力，P沟道SRAM晶体管至少具有比P沟道逻辑晶体管更小的压缩应力，即P沟道SRAM 晶体管可以是压缩的，但是比P沟道逻辑晶体管更小，可以被放宽，或者可以是拉伸的。 P沟道SRAM晶体管的集成电路具有比P沟道逻辑晶体管更低的迁移率是有益的。 具有较低移动性的P沟道SRAM晶体管导致更好的写入性能; 在更低的电源电压下更好地写入时间或写入裕度。

公开(公告)号：US06417539B2

公开(公告)日：2002-07-09

申请号：US09128864

申请日：1998-08-04

申请人： Mark I. Gardner ,  Derick J. Wristers ,  Jon Cheek

发明人： Mark I. Gardner ,  Derick J. Wristers ,  Jon Cheek

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielectric material separates the first electrode form the second electrodes and also separates the second electrodes. Each second electrode forms an individual memory cell associated with the first electrode. The memory cell assembly can be made by, first, forming a first electrode over a substrate. A second electrode layer is formed over the first electrode. The second electrode layer includes two or more second electrodes. A dielectric material is formed between the first electrode and the second electrodes and between the second electrodes.

摘要翻译： 存储单元组件包括衬底，第一电极和第二电极层。 第一电极设置在衬底上，并且第二电极层设置在第一电极上。 第二电极层包括两个或更多个第二电极。 电介质材料将第一电极与第二电极分开，并分离第二电极。 每个第二电极形成与第一电极相关联的单个存储单元。 存储单元组件可以通过首先在衬底上形成第一电极来制造。 在第一电极上形成第二电极层。 第二电极层包括两个或更多个第二电极。 在第一电极和第二电极之间以及第二电极之间形成电介质材料。

公开(公告)号：US5970349A

公开(公告)日：1999-10-19

申请号：US139179

申请日：1998-08-24

申请人： Jon Cheek ,  Mark I. Gardner ,  Michael Duane

发明人： Jon Cheek ,  Mark I. Gardner ,  Michael Duane

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/266

CPC分类号： H01L29/66659 ,  H01L29/1083

摘要： Semiconductor devices having one or more asymmetric background dopant regions and methods of fabrication thereof are provided. The asymmetric background dopant regions may be formed using a patterned mask with wider openings than conventional masks while substantially maintaining device performance. This can, for example, facilitate the fabrication process and allow greater flexibility in the choice of photolithography tools.

摘要翻译： 提供具有一个或多个不对称背景掺杂剂区域的半导体器件及其制造方法。 可以使用具有比常规掩模更宽的开口的图案化掩模来形成不对称背景掺杂区域，同时基本上保持器件性能。 例如，这可以促进制造工艺并且允许在光刻工具的选择中具有更大的灵活性。

公开(公告)号：US5935766A

公开(公告)日：1999-08-10

申请号：US908487

申请日：1997-08-07

申请人： Jon Cheek ,  Daniel Kadosh ,  Derick J. Wristers

发明人： Jon Cheek ,  Daniel Kadosh ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L23/522 ,  G03F7/00 ,  H01L21/02

CPC分类号： H01L23/5226 ,  H01L21/76838 ,  H01L2924/0002

摘要： A method of forming a conductive plug in an interlevel dielectric includes forming a lower dielectric layer over a semiconductor substrate. A first etch mask is formed over the lower dielectric layer and is patterned using a reticle. A first etch is applied through an opening in the first etch mask to form an opening in the lower dielectric layer. A lower conductor is formed in the opening in the lower dielectric layer. A conducting layer is formed over the lower dielectric layer and the lower conductor. A second etch mask is formed over the conducting layer and is patterned using the reticle. A second etch is applied through an opening in the second etch mask to form a contact pad from an unetched portion of the conducting layer. An upper dielectric layer is formed over the lower dielectric layer and the contact pad. A third etch mask is formed over the upper dielectric layer and is patterned using the reticle. A third etch is applied through an opening in the third etch mask to form an opening in the upper dielectric layer. An upper conductor is formed in the opening in the upper dielectric layer. As a result, the conductive plug includes the upper and lower conductors and the contact pad, and the interlevel dielectric includes the upper and lower dielectric layers.

摘要翻译： 在层间电介质中形成导电插塞的方法包括在半导体衬底上形成下介电层。 在下介电层上形成第一蚀刻掩模，并使用掩模版进行图案化。 通过第一蚀刻掩模中的开口施加第一蚀刻，以在下介电层中形成开口。 下导体形成在下电介质层的开口中。 在下介电层和下导体上形成导电层。 在导电层上形成第二蚀刻掩模，并使用掩模版进行图案化。 通过第二蚀刻掩模中的开口施加第二蚀刻，以从导电层的未蚀刻部分形成接触焊盘。 在下电介质层和接触焊盘上形成上介电层。 在上电介质层上形成第三蚀刻掩模，并使用掩模版进行图案化。 通过第三蚀刻掩模中的开口施加第三蚀刻，以在上介电层中形成开口。 上导体形成在上电介质层的开口中。 结果，导电插塞包括上导体和下导体和接触垫，并且层间电介质包括上和下介电层。

公开(公告)号：US07208383B1

公开(公告)日：2007-04-24

申请号：US10284651

申请日：2002-10-30

申请人： Chad Weintraub ,  James F. Buller ,  Derick Wristers ,  Jon Cheek

发明人： Chad Weintraub ,  James F. Buller ,  Derick Wristers ,  Jon Cheek

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659

摘要： An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain extension region are formed in a semiconductor material using an angled implant. The source extension region extends under the gate structure, whereas the drain extension region is laterally spaced apart from the gate structure. A source region is formed in the semiconductor substrate and a drain region is formed in the semiconductor substrate, where the source and drain regions are laterally spaced apart from the gate structure. A source-side halo region is formed in the semiconductor substrate adjacent the source extension region.

摘要翻译： 具有减小的栅 - 漏重叠的绝缘栅场效应晶体管和用于制造绝缘栅场效应晶体管的方法。 栅极结构形成在半导体衬底的主表面上。 源极延伸区域和漏极延伸区域使用成角度的植入物形成在半导体材料中。 源极延伸区域在栅极结构下方延伸，而漏极延伸区域与栅极结构横向间隔开。 源极区域形成在半导体衬底中，并且在半导体衬底中形成漏极区域，其中源极区域和漏极区域与栅极结构横向间隔开。 源极侧晕区形成在与源延伸区相邻的半导体衬底中。

公开(公告)号：US06242330B1

公开(公告)日：2001-06-05

申请号：US08994200

申请日：1997-12-19

申请人： Jon Cheek ,  Derick J. Wristers ,  Fred Hause

发明人： Jon Cheek ,  Derick J. Wristers ,  Fred Hause

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： A process for breaking silicide stringers extending between silicide regions of different active regions on a semiconductor device is provided. Consistent with an exemplary fabrication process, two adjacent silicon active regions are formed on a substrate and a metal layer is formed over the two adjacent silicon active regions. The metal layer is then reacted with the silicon active regions to form a metal silicide on each silicon active region. This silicide reaction also forms silicide stringers extending from each silicon active region. Finally, at least part of each silicide stringer is removed. During the formation of the silicide stringers at least one silicide stringer may be formed which bridges the metal silicide over one of the silicon regions and the metal silicide over the other silicon region. In such circumstances, the removal process may, for example, break the silicide stringer and electrically decouple the two silicon regions. The two silicon active regions may, for example, be a gate electrode and an adjacet source/drain region. As another example, the two adjacent active regions may be two nearby polysilicon lines.

摘要翻译： 提供了一种用于在半导体器件上破坏在不同有源区的硅化物区之间延伸的硅化物桁条的工艺。 与示例性制造工艺一致，在衬底上形成两个相邻的硅有源区，并且在两个相邻的硅有源区上形成金属层。 然后金属层与硅有源区反应，以在每个硅有源区上形成金属硅化物。 这种硅化物反应也形成从每个硅活性区延伸的硅化物桁条。 最后，每个硅化物纵梁的至少部分被去除。 在硅化物桁条的形成期间，可以形成至少一个硅化物桁条，其将金属硅化物跨过其中一个硅区域和金属硅化物超过另一个硅区域。 在这种情况下，移除过程可能会例如破坏硅化物纵梁并使两个硅区域电耦合。 两个硅有源区可以例如是栅电极和辅助源/漏区。 作为另一示例，两个相邻的有源区可以是两个附近的多晶硅线。

公开(公告)号：US6110786A

公开(公告)日：2000-08-29

申请号：US61409

申请日：1998-04-16

申请人： Mark I. Gardner ,  Jon Cheek ,  John Bush

发明人： Mark I. Gardner ,  Jon Cheek ,  John Bush

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/66636 ,  H01L29/78

摘要： A semiconductor device having an elevated gate electrode and elevated active regions and a process for manufacturing such a device is disclosed. In accordance with one embodiment a semiconductor device is formed by forming a gate insulating layer over a substrate and forming a photoresist block over the gate insulating layer. First portions of the gate insulating layer and first portions of the substrate adjacent the photoresist block are then removed to form a first elevated substrate region under the gate insulating layer and photoresist block. Edge portions of the photoresist block are then removed. Second portions of the gate insulating layer and portions of the first elevated substrate region adjacent the photoresist block are then removed to form second elevated substrate regions adjacent the photoresist block, and a dopant is implanted into the second elevated substrate regions to form source/drain regions, and the photoresist block is used to form a gate electrode. In accordance with another embodiment a semiconductor device is formed substantially as above, but the dopant is implanted at an angle relative to the substrate surface.

摘要翻译： 公开了一种具有升高的栅电极和升高的有源区的半导体器件及其制造方法。 根据一个实施例，通过在衬底上形成栅极绝缘层并在栅极绝缘层上形成光致抗蚀剂阻挡层来形成半导体器件。 然后去除栅极绝缘层的第一部分和与光致抗蚀剂嵌段相邻的基板的第一部分，以在栅极绝缘层和光致抗蚀剂阻挡块下方形成第一升高的基板区域。 然后去除光致抗蚀剂块的边缘部分。 然后去除栅极绝缘层的第二部分和邻近光致抗蚀剂阻挡块的第一升高的衬底区域的部分，以形成与光致抗蚀剂阻挡层相邻的第二升高的衬底区域，并且将掺杂剂注入第二升高的衬底区域以形成源极/漏极区域 ，并且光致抗蚀剂块用于形成栅电极。 根据另一个实施例，基本上如上所述形成半导体器件，但掺杂剂以相对于衬底表面成一角度注入。

公开(公告)号：US6075417A

公开(公告)日：2000-06-13

申请号：US2655

申请日：1998-01-05

申请人： Jon Cheek ,  Antonio Garcia ,  John Bush

发明人： Jon Cheek ,  Antonio Garcia ,  John Bush

IPC分类号： G01R31/28 ,  H03B5/24 ,  G01R31/00

CPC分类号： G01R31/2824

摘要： An improved oscillator test structure is disclosed. A structure according to one embodiment includes an odd plurality of first transistor pairs formed on a predetermined area of a semiconductor substrate. The transistor pairs are electrically connected in a serial ring. The structure also includes at least one second transistor pair, also formed within the predetermined area on the substrate, but electrically isolated from the odd plurality of first transistor pairs.

摘要翻译： 公开了一种改进的振荡器测试结构。 根据一个实施例的结构包括形成在半导体衬底的预定区域上的奇数个第一晶体管对。 晶体管对以串联环电连接。 该结构还包括至少一个第二晶体管对，其也形成在衬底上的预定区域内，但与奇数多个第一晶体管对电隔离。

公开(公告)号：US5976925A

公开(公告)日：1999-11-02

申请号：US980636

申请日：1997-12-01

申请人： Jon Cheek ,  Derick J. Wristers ,  James F. Buller

发明人： Jon Cheek ,  Derick J. Wristers ,  James F. Buller

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/823418 ,  H01L29/665

摘要： A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a polysilicon layer is formed over the substrate. The polysilicon layer is then implanted with a first dopant to form a doped polysilicon layer. Portions of the doped polysilicon layer are then removed to form at least one gate electrode. Active regions of the substrate adjacent the gate electrode are implanted with a second dopant to form source/drain regions in the substrate. In this manner, the implant used to form the source/drain regions may be decoupled from the implant used to form the gate electrode. This, for example, allows for shallower source/drain regions to be formed without the formation of the depletion layer in the gate electrode.

摘要翻译： 提供具有非对称掺杂的栅电极和有源区的半导体器件和制造这种器件的工艺。 根据本发明的一个实施例，在衬底上形成多晶硅层。 然后用第一掺杂剂注入多晶硅层以形成掺杂多晶硅层。 然后去除掺杂多晶硅层的部分以形成至少一个栅电极。 与栅电极相邻的衬底的有源区注入第二掺杂剂以在衬底中形成源极/漏极区。 以这种方式，用于形成源极/漏极区域的植入物可以与用于形成栅电极的植入物去耦合。 例如，这允许形成更浅的源/漏区，而不在栅电极中形成耗尽层。