MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF
    21.
    发明申请
    MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF 有权
    存储器电路布置及其生产方法

    公开(公告)号:US20090052219A1

    公开(公告)日:2009-02-26

    申请号:US12258728

    申请日:2008-10-27

    IPC分类号: G11C5/02 G11C5/06 H01L21/00

    摘要: A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

    摘要翻译: 提出了一种存储器电路装置及其制造方法,其中存储器电路装置的部件位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一(逻辑电路)基板上。 当读取,写入或擦除存储单元的内容时,控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器,借助于此可以确定存储器单元的存储状态,以及选择字或位线的解码电路。

    Configurable logic component without a local configuration memory and with a parallel configuration bus
    22.
    发明授权
    Configurable logic component without a local configuration memory and with a parallel configuration bus 有权
    可配置逻辑组件,无需本地配置存储器和并行配置总线

    公开(公告)号:US07348795B2

    公开(公告)日:2008-03-25

    申请号:US11032436

    申请日:2005-01-10

    IPC分类号: H03K19/173

    摘要: A configurable logic component (30) does not have a local configuration memory. The configuration of the configurable logic component is defined by applied voltages. The configuration voltages are advantageously generated in an external configuration memory (2). In one preferred refinement, a memory chip (20) (for example EEPROM) and the inventive logic component without a configuration memory (30) are mounted face-to-face. An intermediate, structured solder layer (40) makes available a plurality of electrical connections.

    摘要翻译: 可配置逻辑组件(30)没有本地配置存储器。 可配置逻辑组件的配置由施加的电压定义。 配置电压有利地在外部配置存储器(2)中产生。 在一个优选的改进中,面对面地安装存储芯片(20)(例如EEPROM)和没有配置存储器(30)的本发明的逻辑组件。 中间结构化的焊料层(40)可提供多个电连接。

    Preparation of homopolymers and copolymers of propylene by means of a
Ziegler-Natta catalyst system
    23.
    发明授权
    Preparation of homopolymers and copolymers of propylene by means of a Ziegler-Natta catalyst system 失效
    通过齐格勒 - 纳塔催化剂体系制备丙烯的均聚物和共聚物

    公开(公告)号:US4761461A

    公开(公告)日:1988-08-02

    申请号:US930529

    申请日:1986-11-14

    CPC分类号: C08F10/06 Y10S526/901

    摘要: Polymers of polypropylene are prepared by means of a Ziegler-Natta catalyst system comprising (1) a titanium component which contains titanium, magnesium, chlorine and a benzenecarboxylic acid derivative, (2) an aluminum component and (3) a silane component, wherein the (1) used is obtained by (1.1) first reacting with one another (1.1.1) in a liquid hydrocarbon, (1.1.2) a finely divided magnesium halide, (1.1.3) an alkanol, (1.1.4) a phthalic acid ester and (1.1.5) titanium tetrachloride under certain conditions, (1.2) then extracting the solid intermediate obtained from (1.1) with titanium tetrachloride until the remaining solid substance has become significantly richer in magnesium, and (1.3) finally washing the solid substance remaining in (1.2) with an alkane in a certain manner.

    摘要翻译: 聚丙烯的聚合物通过齐格勒 - 纳塔催化剂体系制备,该系统包括(1)钛,镁,氯和苯甲酸衍生物的钛组分,(2)铝组分和(3)硅烷组分,其中 (1.1)通过(1.1)在液体烃中首先反应(1.1.1)获得,(1.1.2)细碎的卤化镁,(1.1.3)链烷醇,(1.1.4)a 邻苯二甲酸酯和(1.1.5)四氯化钛,(1.2),然后用四氯化钛萃取由(1.1)得到的固体中间体,直到剩下的固体物质变得更加富镁,(1.3)最后洗涤 残留在(1.2)中的固体物质以某种方式与烷烃反应。

    Preparation of homopolymers and copolymers of .alpha.-monoolefins using
a Ziegler-Natta catalyst system
    25.
    发明授权
    Preparation of homopolymers and copolymers of .alpha.-monoolefins using a Ziegler-Natta catalyst system 失效
    使用齐格勒 - 纳塔催化剂体系制备α-单烯烃的均聚物和共聚物

    公开(公告)号:US4579919A

    公开(公告)日:1986-04-01

    申请号:US673337

    申请日:1984-11-20

    CPC分类号: C08F10/00

    摘要: .alpha.-Monoolefins are polymerized using a catalyst system which comprises (1) a titanium component obtained by first (1.a) preparing an intermediate from (1.a.1) titanium tetrachloride, (1.a.2) a modifier and (1.a.3) a magnesium alcoholate, and the (1.b) preparing the titanium component from (1.b.1) titanium tetrachloride, (1.b.2) the intermediate from (1.a) and, if required, (1.b.3) a further modifier, (2) an alkylaluminum and (3) a cocatalyst. In this process, (i) the titanium component (1) used is obtained by first (1.1) preparing a first intermediate from (1.1.1) titanium tetrachloride, (1.1.2) a modifier obtained from (1.1.2.1) a titanate and (1.1.2.2) a phthaloyl dichloride, and (1.1.3) a magnesium alcoholate, then (1.2) preparing a second intermediate from (1.2.1) titanium tetrachloride, (1.2.2) the intermediate from (1.1) and, if required, (1.2.3) a phthaloyl dichloride as a further modifier, and finally (1.3) preparing the titanium component from (1.3.1) titanium tetrachloride and (1.3.2) the intermediate from (1.2), and (ii) the cocatalyst (3) used is a trialkoxysilane.

    摘要翻译: α-烯烃使用催化剂体系进行聚合,所述催化剂体系包括(1)通过首先(1.a)从(1.a)四氯化钛制备中间体,(1.a.2)改性剂和( 1.a.3)一种醇镁,和(1.b)从(1.b.1)四氯化钛制备钛组分,(1.b.2)中间体为(1.a),如果 (1.b.3)另一种改性剂,(2)烷基铝和(3)助催化剂。 在该方法中,(i)使用的钛组分(1)首先(1.1)由(1.1.1)四氯化钛制备第一中间体,(1.1.2)由(1.1.2.1)得到的改性剂钛酸酯 和(1.1.2.2)邻苯二甲酰二氯化物,和(1.1.3)醇镁酸盐,然后(1.2)从(1.1.1)四氯化钛(1.2.1)制备第二中间体,(1.2.2)(1.1)中间体, (1.2.3)邻苯二甲酰二氯作为其他改性剂,最后(1.3)从(1.3.1)四氯化钛制备钛组分和(1.3.2)中间体(1.2)和(ii) 所用的助催化剂(3)是三烷氧基硅烷。

    NADH Peroxidase for hydrogen peroxide determination
    27.
    发明授权
    NADH Peroxidase for hydrogen peroxide determination 失效
    NADH过氧化物酶测定过氧化氢

    公开(公告)号:US4186052A

    公开(公告)日:1980-01-29

    申请号:US811422

    申请日:1977-06-29

    CPC分类号: C12N9/0065 C12Q1/28

    摘要: A novel peroxidase for reduced nicotinamide-adenine-dinucleotide is provided which peroxidase oxidizes reduced nicotinamide-adenine-dinucleotide with hydrogen peroxide to give nicotinamide-adenine-dinucleotide and water and is characterized by a Michaelis constant K.sub.Mto hydrogen peroxide of 2.8.times.10.sup.-5 M andto reduced nicotinamide-adenine-dinucleotide of 1.7.times.10.sup.-5 M,measured at 25.degree. C. in 0.2M tris buffer of pH 6.0, containing 0.1M potassium acetate. The peroxidase can be prepared by liberating the enzyme from Streptococcus faecalis ATCC 8043 by digestion or by treatment with a surface-active agent and isolating same from the enzyme solution obtained. Hydrogen peroxide is determined in a simple reaction or in a coupled reaction with a specific oxidase by contacting the said peroxidase with the H.sub.2 O.sub.2 producing reaction mixture at a pH of from 6.0 to 9.0 and measuring the change of extinction as a measure of H.sub.2 O.sub.2 and of the concentration of nicotinamide-adenine-dinucleotide initially present in said reaction mixture.

    摘要翻译: 提供了一种用于还原型烟酰胺 - 腺嘌呤二核苷酸的新型过氧化物酶,其过氧化物酶用过氧化氢氧化还原型烟酰胺 - 腺嘌呤二核苷酸,得到烟酰胺 - 腺嘌呤二核苷酸和水,其特征在于具有2.8x10-5M的过氧化氢的米氏常数KM, 降低了1.7×10-5M的烟酰胺 - 腺嘌呤二核苷酸,在25℃下,在含有0.1M醋酸钾的0.2M Tris缓冲液pH6.0中测定。 过氧化物酶可以通过消化或通过用表面活性剂处理从粪链球菌ATCC 8043中释放酶制备,并从获得的酶溶液中分离。 过氧化氢在简单的反应或与特定氧化酶的偶联反应中通过使所述过氧化物酶与产生H 2 O 2的反应混合物在6.0至9.0的pH下接触并测定作为H 2 O 2和 最初存在于所述反应混合物中的烟酰胺 - 腺嘌呤二核苷酸的浓度。

    Memory circuit arrangement with a cell array substrate and a logic circuit substrate and method for the production thereof
    29.
    发明授权
    Memory circuit arrangement with a cell array substrate and a logic circuit substrate and method for the production thereof 有权
    具有单元阵列基板和逻辑电路基板的存储器电路布置及其制造方法

    公开(公告)号:US07460385B2

    公开(公告)日:2008-12-02

    申请号:US11251355

    申请日:2005-10-14

    IPC分类号: G11C5/02 G11C5/06

    摘要: In a memory circuit arrangement and fabrication method, the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

    摘要翻译: 在存储器电路布置和制造方法中,存储器电路装置的部分位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一(逻辑电路)基板上。 当读取,写入或擦除存储单元的内容时,控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器,借助于此可以确定存储器单元的存储状态,以及选择字或位线的解码电路。

    Configurable logic component without a local configuration memory and with a parallel configuration bus
    30.
    发明申请
    Configurable logic component without a local configuration memory and with a parallel configuration bus 有权
    可配置逻辑组件,无需本地配置存储器和并行配置总线

    公开(公告)号:US20050184755A1

    公开(公告)日:2005-08-25

    申请号:US11032436

    申请日:2005-01-10

    IPC分类号: H03K19/173 H03K19/177

    摘要: A configurable logic component (30) does not have a local configuration memory. The configuration of the configurable logic component is defined by applied voltages. The configuration voltages are advantageously generated in an external configuration memory (2). In one preferred refinement, a memory chip (20) (for example EEPROM) and the inventive logic component without a configuration memory (30) are mounted face-to-face. An intermediate, structured solder layer (40) makes available a plurality of electrical connections.

    摘要翻译: 可配置逻辑组件(30)没有本地配置存储器。 可配置逻辑组件的配置由施加的电压定义。 配置电压有利地在外部配置存储器(2)中产生。 在一个优选的改进中,面对面地安装存储芯片(20)(例如EEPROM)和没有配置存储器(30)的本发明的逻辑组件。 中间结构化的焊料层(40)可提供多个电连接。