公开(公告)号：US20100310934A1

公开(公告)日：2010-12-09

申请号：US12632761

申请日：2009-12-07

申请人： Chun-Mo Yang ,  Kasai Masahiro ,  Sung-Hoon Kim

发明人： Chun-Mo Yang ,  Kasai Masahiro ,  Sung-Hoon Kim

IPC分类号： H01M4/00 ,  H01B1/02

CPC分类号： H01M4/131 ,  H01M4/364 ,  H01M4/505 ,  H01M4/525

摘要： A positive electrode for a rechargeable lithium battery includes a first positive active material represented by LiaNibCOcMdO2, and a second positive active material represented by LieNifCOgMnhO2. M is selected from Al, B, Cr, Fe, Mg, Sr, and V, 0.95≦a≦1.1, 0.5≦b≦0.9, 0≦c≦0.3, 0≦d≦0.1, 0.95≦e≦1.1, 0.33≦f≦0.5, 0.15≦g≦0.33, and 0.3≦h≦0.35. A rechargeable lithium battery includes the positive electrode, a negative electrode and an electrolyte.

摘要翻译： 用于可再充电锂电池的正电极包括由LiaNibCOcMdO 2表示的第一正极活性材料和由LieNifCOgMnhO2表示的第二正极活性材料。 M选自Al，B，Cr，Fe，Mg，Sr和V，0.95＆nlE; a＆nlE; 1.1,0.5＆nlE; b＆nlE; 0.9,0和nlE; c＆nlE; 0.3,0和nlE; d＆nlE; 0.1,0.95＆ 1.1,0.33＆nlE; f＆nlE; 0.5,0.15＆nlE; g＆nlE; 0.33和0.3＆amp; nlE; h＆nlE; 0.35。 可充电锂电池包括正极，负极和电解质。

公开(公告)号：US07779327B2

公开(公告)日：2010-08-17

申请号：US10594467

申请日：2005-04-01

申请人： Jae-Young Lee ,  Kum-Ran Ji ,  Sung-Hoon Kim ,  Seung-Won Kim ,  Soo-In Lee ,  Chieteuk Ahn

发明人： Jae-Young Lee ,  Kum-Ran Ji ,  Sung-Hoon Kim ,  Seung-Won Kim ,  Soo-In Lee ,  Chieteuk Ahn

IPC分类号： H03M13/29

CPC分类号： H03M13/256 ,  H03M13/253 ,  H03M13/2732 ,  H03M13/2936 ,  H03M13/356 ,  H04L1/0057 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/007 ,  H04L1/0071

摘要： Provided are a Vestigial Side Band (VSB) Digital Television (DTV) transmitter and receiver based on the Advanced Television System Committee (ATSC) A/53, and a method thereof. The present invention provides 8-VSB DTV transmitter and receiver that can improve reception performance of the receiver by transmitting and receiving robust data mixed with P-2VSB, E-4VSB, and/or E-8VSB. The DTV transmitter includes an input means for receiving a digital video data stream including normal data and robust data; an encoding means for coding the digital video data stream into data symbols; and a transmitting means for modulating and transmitting an output signal of the encoding means, wherein the encoding means performs trellis coding on the robust data by sequentially applying a plurality of trellis coding methods.

摘要翻译： 提供了基于高级电视系统委员会（ATSC）A / 53的残留边带（VSB）数字电视（DTV）发射机和接收机及其方法。 本发明提供了通过发送和接收与P-2VSB，E-4VSB和/或E-8VSB混合的鲁棒数据来提高接收机的接收性能的8-VSB DTV发射机和接收机。 DTV发射机包括用于接收包括正常数据和鲁棒数据的数字视频数据流的输入装置; 用于将数字视频数据流编码成数据符号的编码装置; 以及发送装置，用于调制和发送编码装置的输出信号，其中编码装置通过顺序地应用多个网格编码方法对鲁棒数据执行格状编码。

公开(公告)号：US07525173B2

公开(公告)日：2009-04-28

申请号：US11485341

申请日：2006-07-13

申请人： Hyang-Ja Yang ,  Su-Jin Park ,  Uk-Rae Cho ,  Sung-Hoon Kim

发明人： Hyang-Ja Yang ,  Su-Jin Park ,  Uk-Rae Cho ,  Sung-Hoon Kim

IPC分类号： H01L29/78

CPC分类号： H01L27/0203 ,  H01L21/823418 ,  H01L21/823481

摘要： In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench isolation, and a second group of MOS transistors having second drain regions and second source regions allocated to the group active region. The second group is disposed between the first group and an edge of the group active region. One or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode.

摘要翻译： 在多个金属氧化物半导体（MOS）晶体管的布局结构中，布局结构可以包括具有第一漏极区域的第一组MOS晶体管和分别分配给与所有侧面隔离的组有源区域的第一源极区域 通过沟槽隔离，以及第二组MOS晶体管，其具有分配给组有源区的第二漏极区和第二源极区。 第二组布置在第一组与组有源区的边缘之间。 第一漏极区域和第一源极区域中的一个或两个不与指状栅电极的长度方向上的沟槽隔离边缘接触。

公开(公告)号：US07463493B2

公开(公告)日：2008-12-09

申请号：US11304014

申请日：2005-12-14

申请人： Chi-Seob Sim ,  Sung-Hoon Kim

发明人： Chi-Seob Sim ,  Sung-Hoon Kim

IPC分类号： H05K1/11

CPC分类号： H05K13/0061 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/53174 ,  Y10T29/53178

摘要： A module for transferring a PCB including a first transfer body that is translatable along a first moving path to transfer a first PCB and a second transfer body that is translatable along a second moving path to transfer a second PCB with the second transfer body being formed with an aperture therein. Additionally the first transfer body is adjustable from a first position where the first transfer body does not fit through the aperture to a second position wherein the first transfer body can fit within the aperture.

摘要翻译： 一种用于传送PCB的模块，其包括可沿着第一移动路径平移以传送第一PCB的第一传送体和可沿着第二移动路径平移的第二传送体，以便与第二传送体一起传送第二PCB， 其中的孔。 另外，第一传送体可从第一传送体不穿过孔的第一位置调节到第二位置，其中第一传送体可装配在孔内。

公开(公告)号：US07450611B2

公开(公告)日：2008-11-11

申请号：US10266106

申请日：2002-10-07

申请人： Sung-Hoon Kim ,  Kook-Heui Lee ,  Ju-Ho Lee ,  Sung-Ho Choi

发明人： Sung-Hoon Kim ,  Kook-Heui Lee ,  Ju-Ho Lee ,  Sung-Ho Choi

IPC分类号： H04J3/16 ,  H04J3/22

CPC分类号： H04L1/0017 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0013 ,  H04L1/0026 ,  H04L1/1812 ,  H04L69/04

摘要： An HSDPA (High Speed Downlink Packet Access) communication system is disclosed. A Node B reduces a size of a field transmitting TBS (Transport Block Set) information for user data based on an MCS (Modulation and Coding Scheme) level assigned to the user data and the number of codes assigned to the user data, before transmission, instead of transmitting an intact size of the actually transmitted transport block for the user data, among TFRI (Transport Format Resource Information) transmitted to a UE (User Equipment) over a shared control channel.

摘要翻译： 公开了一种HSDPA（高速下行链路分组接入）通信系统。 基于在发送之前分配给用户数据的MCS（调制和编码方案）级别和分配给用户数据的代码数量，节点B减小用于用户数据的字段传输TBS（传输块集）信息的大小， 而不是在通过共享控制信道发送给UE（用户设备）的TFRI（传输格式资源信息）中发送用于用户数据的实际发送的传输块的完整大小。

公开(公告)号：US07442448B2

公开(公告)日：2008-10-28

申请号：US11033403

申请日：2005-01-12

申请人： Kwang-Hyun Kim ,  Dong-Uk Kim ,  Tae-Jeong Kim ,  Ung-Chan Yoon ,  Sung-Hoon Kim ,  Ki-Dong Kim

发明人： Kwang-Hyun Kim ,  Dong-Uk Kim ,  Tae-Jeong Kim ,  Ung-Chan Yoon ,  Sung-Hoon Kim ,  Ki-Dong Kim

IPC分类号： H01L51/54 ,  C09K11/06

CPC分类号： C07F15/0033 ,  Y10S428/917

摘要： The present invention relates to emitting compounds for organic electroluminescent device, particularly to phenyl pyridine-iridium metal complex compounds represented by the following formula (1): wherein R1 to R8, A1 to A3, and Py are as defined in the specification. In addition, the present invention relates to an organic electroluminescent device comprising the above material which has high luminescence efficiency, enhanced operating life time, and high purity of red chromaticity.

摘要翻译： 本发明涉及用于有机电致发光器件的发光化合物，特别涉及由下式（1）表示的苯基吡啶 - 铱金属络合物：其中R 1至R 8 - A 1，A 3，和Py如说明书中所定义。 此外，本发明涉及包含上述材料的有机电致发光器件，其具有高发光效率，增加的使用寿命和高纯度的红色度。

公开(公告)号：US20070030051A1

公开(公告)日：2007-02-08

申请号：US11472850

申请日：2006-06-22

申请人： Yu-Lim Lee ,  Sung-Hoon Kim

发明人： Yu-Lim Lee ,  Sung-Hoon Kim

IPC分类号： H01H37/76

CPC分类号： H01L23/585 ,  G11C29/028 ,  G11C29/50008 ,  G11C2029/4402 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature information; a signature output circuit configured to block the signature signal output by the signature program circuit during operation in a normal mode, and configured to pass the signature signal during operation in a test mode; and a pad-driving transistor directly coupled to the pad, configured to drive the pad during operation in the normal mode in response to an operation command, and configured to drive the pad during operation in the test mode in response to the signature signal output by the signature output circuit. The signature circuit outputs the signature information through a transistor for adjusting impedance to reduce a chip size by omitting an additional logic circuit for the signature circuit.

摘要翻译： 半导体芯片中的签名电路包括签名程序电路，其被配置为对签名信息进行编程，并响应于签名信息输出签名信号; 签名输出电路，被配置为在正常模式下操作期间阻止由所述签名程序电路输出的签名信号，并且被配置为在测试模式下操作期间传递所述签名信号; 以及焊盘驱动晶体管，其直接耦合到所述焊盘，被配置为响应于操作命令在正常模式下操作期间驱动焊盘，并且被配置为响应于在测试模式中的操作期间响应于由 签名输出电路。 签名电路通过用于调整阻抗的晶体管输出签名信息，以通过省略签名电路的附加逻辑电路来减小芯片尺寸。

公开(公告)号：US07161823B2

公开(公告)日：2007-01-09

申请号：US11134855

申请日：2005-05-19

申请人： Jae-Young Lee ,  Joon-Hyuk Kwon ,  Chi-Wook Kim ,  Sung-Hoon Kim ,  Youn-Sik Park

发明人： Jae-Young Lee ,  Joon-Hyuk Kwon ,  Chi-Wook Kim ,  Sung-Hoon Kim ,  Youn-Sik Park

IPC分类号： G11C5/06

CPC分类号： G11C5/14 ,  G11C5/063 ,  G11C11/4074

摘要： Method and apparatus for use, e.g., with Synchronous Dynamic Random Access Memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.

摘要翻译： 公开了使用例如同步动态随机存取存储器（SDRAM）电路的方法和装置。 在一个所描述的实施例中，沉积三层金属层并依次叠置在SDRAM的存储器阵列部分上。 相对宽的电力导体在第三金属层上布线，允许在第一和第二金属层上的电力导体的尺寸减小或在某些情况下被消除。 因此，相对宽的电力导体可以向存储器阵列提供更稳定的电源，并且还释放第一和/或第二金属上的一些空间，用于路由额外的和/或更广泛间隔的信号导体。 描述和要求保护其他实施例。

公开(公告)号：US20060077748A1

公开(公告)日：2006-04-13

申请号：US11232175

申请日：2005-09-21

申请人： Sung-Hoon Kim ,  Joung-Yeal Kim

发明人： Sung-Hoon Kim ,  Joung-Yeal Kim

IPC分类号： G11C8/00

CPC分类号： G11C8/06

摘要： An address buffer circuit for a semiconductor memory device wherein an address buffer is enabled (to output an internal address signal) in response to a first level of a control signal and, but is disabled in response to a second level of the control signal. An address buffer control unit generates the control signal at the second level in ‘no operation’ state (NOP command) in which the semiconductor memory device does not perform data accessing operations and generates the control signal at the first level while the semiconductor memory device performs data accessing operations, thereby reducing or minimizing the output of an internal address buffered and output by the address buffer at and thus reducing power consumption during no-operation states of the semiconductor memory device.

公开(公告)号：US5953270A

公开(公告)日：1999-09-14

申请号：US153343

申请日：1998-09-15

申请人： Sung-Hoon Kim

发明人： Sung-Hoon Kim

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/806

摘要： The present invention relates to a column redundancy circuit in semiconductor memories which improves yields by means of substituting defective cells with redundant memory cells provided that defective memory cells are detected. The present invention of a redundancy circuit in semiconductor memories having a first memory cell array and a second memory cell arrays with an Y-decoder includes a first row redundancy circuit receiving a row address signal wherein the first row redundancy circuit outputs a first MAT selection signal for repairing a word line in the first memory cell array, a second row redundancy circuit receiving the row address signal wherein the second row to redundancy circuit outputs a second MAT selection signal for repairing a word line in the second memory cell array, a redundancy circuit controller generating a first MAT selection enable signal and a second MAT selection enable signal wherein the first MAT selection enable signal and the second MAT selection enable signal are complementary each other, a MAT selection signal controller receiving the first MAT selection signal and the second MAT selection signal wherein the MAT selection signal controller outputs one of the first MAT selection signal and the second MAT selection signal in accordance with the first MAT selection enable signal and the second MAT selection enable signal, respectively, a column redundancy circuit receiving a column address signal and the MAT selection signal which is outputted from the MAT selection signal controller wherein the column redundancy circuit outputs a repairing decision signal, a first MAT redundant signal and a second MAT redundant signal, and an Y-decoder receiving the first MAT redundant signal and the second MAT redundant signal wherein the Y-decoder outputs a normal column selection signal or a redundant column selection signal under a condition of the repairing decision signal.

摘要翻译： 半导体存储器中的列冗余电路技术领域本发明涉及半导体存储器中的列冗余电路，其通过用冗余存储器单元替换有缺陷的单元来提高产量，只要检测到有缺陷的存储单元即可。 具有第一存储单元阵列的半导体存储器中的冗余电路的本发明和具有Y解码器的第二存储单元阵列的本发明包括：第一行冗余电路，其接收行地址信号，其中第一行冗余电路输出第一MAT选择信号 用于修复第一存储单元阵列中的字线，接收行地址信号的第二行冗余电路，其中第二行至冗余电路输出用于修复第二存储单元阵列中的字线的第二MAT选择信号，冗余电路 控制器生成第一MAT选择使能信号和第二MAT选择使能信号，其中第一MAT选择使能信号和第二MAT选择使能信号彼此互补; MAT选择信号控制器，接收第一MAT选择信号和第二MAT选择 信号，其中所述MAT选择信号控制器输出所述第一MAT选择中的一个 n信号和第二MAT选择信号，分别根据第一MAT选择使能信号和第二MAT选择使能信号，接收列地址信号的列冗余电路和从MAT选择信号控制器输出的MAT选择信号 其中所述列冗余电路输出修复决定信号，第一MAT冗余信号和第二MAT冗余信号，以及接收所述第一MAT冗余信号和所述第二MAT冗余信号的Y解码器，其中所述Y解码器输出正常列选择 信号或冗余列选择信号。