公开(公告)号：US20070064464A1

公开(公告)日：2007-03-22

申请号：US11229527

申请日：2005-09-20

Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

IPC: G11C17/00

CPC classification number: G11C5/147 ,  G11C16/12

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US08264898B2

公开(公告)日：2012-09-11

申请号：US13156763

申请日：2011-06-09

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C7/00

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US20110235412A1

公开(公告)日：2011-09-29

申请号：US13156763

申请日：2011-06-09

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US20100103732A1

公开(公告)日：2010-04-29

申请号：US12650118

申请日：2009-12-30

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US07613044B2

公开(公告)日：2009-11-03

申请号：US11950811

申请日：2007-12-05

Applicant: Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

Inventor： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C7/10

CPC classification number: G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

Abstract translation: 提供了一种用于在半导体存储器件（100）的选定存储单元（200）上进行高性能，高电压存储器操作的方法和装置。 在编程或擦除操作期间，高电压发生器（106）在所选择的字线（502）上提供连续的高电压电平（702），并且向位线解码器（120）保持连续的高电压电平供应，位线解码器（120）依次提供高电压 电平（706）到位线（504）的第一部分，并且在将高电压电平提供给第二部分（710）之前对那些位线（504）进行放电（708）。 为了对编程操作进一步改进，高电压发生器（106）通过在其间提供电流控制装置（1208）来解耦提供给字线（502）和位线（504）的高电压，并在 时间（1104）以克服由与所选位线（504）和/或位线解码器（120）相关联的电容器负载导致的电压电平下降（1102），所述位线（504）的第二部分预充电（1716） 同时向第一部分提供高电压电平以对存储单元（200）的第一部分进行编程（1706）。 为了改进读取操作，动态参考单元（2002）是空白的是通过从第一电压源（2112）到动态参考单元（2002）和从第二电压源（2104）提供非相同调节的高电压电平来确定的 ）到静态参考单元（2004），并且如果动态参考单元（2002）不为空白，则通过向所选择的存储单元（200），动态参考单元（200）提供相同调节的高电压电平来读取所选存储单元（200） 2002）和静态参考单元（2004）。

公开(公告)号：US07352626B1

公开(公告)日：2008-04-01

申请号：US11212614

申请日：2005-08-29

Applicant: Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

Inventor： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

IPC: G11C11/34 ,  G11C7/00

CPC classification number: G11C5/14

Abstract: A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before activating the operational-amplifier section. The capacitor is configured to store charge to supplement current being supplied from the operational-amplifier section. The voltage regulator may be used to supply power to non-volatile memory cells.

Abstract translation: 电压调节器可以包括运算放大器部分，连接到运算放大器部分的输出的电容器和被配置为将电容器连接到电压源的开关。 开关被配置为在激活运算放大器部分之前对电容器充电。 电容器被配置为存储电荷以补充从运算放大器部分提供的电流。 电压调节器可以用于向非易失性存储单元供电。

公开(公告)号：US07307878B1

公开(公告)日：2007-12-11

申请号：US11212850

申请日：2005-08-29

Applicant: Aaron Lee ,  Hounien Chen ,  Sachit Chandra ,  Nancy Leong ,  Guowei Wang

Inventor： Aaron Lee ,  Hounien Chen ,  Sachit Chandra ,  Nancy Leong ,  Guowei Wang

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/0475 ,  G11C16/3454 ,  G11C16/3459

Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收标识阵列中的多个存储单元的编程窗口。 在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。 第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

公开(公告)号：US20070064493A1

公开(公告)日：2007-03-22

申请号：US11229664

申请日：2005-09-20

Applicant: Takao Akaogi ,  Guowei Wang

Inventor： Takao Akaogi ,  Guowei Wang

IPC: G11C16/04

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/10

Abstract: Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.

Abstract translation: 诸如闪存的非易失性存储器通过将信息窗口写入存储器来编程。 可以为每个窗口动态地确定每个存储器单元的编程/非编程状态并将其存储为指示位。 这些技术可以在编程期间提供改善的平均功率消耗和减小每个窗口的最大电流。

公开(公告)号：US06662262B1

公开(公告)日：2003-12-09

申请号：US09420535

申请日：1999-10-19

Applicant: Yasushi Kasa ,  Johnny Chung-Lee Chen ,  Guowei Wang ,  Tiao-Hua Kuo

Inventor： Yasushi Kasa ,  Johnny Chung-Lee Chen ,  Guowei Wang ,  Tiao-Hua Kuo

IPC: G06F1200

CPC classification number: G11C8/12 ,  G11C15/046 ,  G11C16/22

Abstract: A simultaneous operation flash memory capable of providing double protection to An OTP sector. The preferred simultaneous operation flash memory comprises an OTP write-protect CAM, which is in a programmed state if the OTP sector is write-protected. In addition, the preferred simultaneous flash memory further includes an OTP sector lock CAM that is electrically connected with the OTP write-protect CAM. The OTP sector lock CAM is used to lock the OTP write-protect CAM in the programmed state, which, in turn, will designate the OTP sector as read only.

Abstract translation: 同时操作的闪存，能够为OTP扇区提供双重保护。 优选的同时操作闪速存储器包括OTP写保护CAM，如果OTP扇区被写保护，其处于编程状态。 此外，优选的同时闪存还包括与OTP写保护CAM电连接的OTP扇区锁CAM。 OTP扇区锁CAM用于将OTP写保护CAM锁定在编程状态，而后者又将OTP扇区指定为只读。

公开(公告)号：US06397313B1

公开(公告)日：2002-05-28

申请号：US09632390

申请日：2000-08-04

Applicant: Yasushi Kasa ,  Guowei Wang

Inventor： Yasushi Kasa ,  Guowei Wang

IPC: G06F1206

CPC classification number: G11C29/781 ,  G11C2216/22

Abstract: The present invention discloses sector-based redundancy that is capable of making repairs using a plurality of redundant columns of memory cells in a dual bank memory device during simultaneous operation. The simultaneous operation memory device includes a plurality of redundant blocks that can be configured to be located in an upper bank or a sliding lower bank. The redundant blocks are comprised of sectors and each sector contains columns of memory cells. During simultaneous operation, the memory device is capable of reading the columns of memory cells in one bank and writing columns of memory cells in the other bank at the same time. In addition, the simultaneous operation memory device uses sector-based redundancy to repair columns of memory cells that are defective in one bank by electrically exchanging them with redundant columns of memory cells and, at the same time, repair columns of memory cells that are defective in the other bank. The dual bank sector-based redundancy includes a plurality of address CAM circuits that are configurably associated with the redundant blocks based on the bank location of the redundant blocks. The address CAM circuits are configured by a redundancy CAM read drain decoder circuit.

Abstract translation: 本发明公开了基于扇区的冗余，其能够在同时操作期间使用双组存储器设备中的多个冗余列的存储单元进行修复。 同时操作存储装置包括多个冗余块，其可被配置为位于上层或滑动下层。 冗余块由扇区组成，每个扇区包含存储单元列。 在同步操作期间，存储器件能够读取一个存储体中的存储单元的列，并且同时在另一个存储体中写入存储单元的列。 此外，同时操作存储器件使用基于扇区的冗余来通过与存储器单元的冗余列电交换来修复存储单元中有缺陷的存储器单元的列，并且同时修复有缺陷的存储器单元的列 在另一家银行。 基于双银行扇区的冗余包括多个地址CAM电路，其基于冗余块的存储单元位置与冗余块可配置地相关联。 地址CAM电路由冗余CAM读取漏极解码器电路配置。