公开(公告)号：US06662262B1

公开(公告)日：2003-12-09

申请号：US09420535

申请日：1999-10-19

申请人： Yasushi Kasa ,  Johnny Chung-Lee Chen ,  Guowei Wang ,  Tiao-Hua Kuo

发明人： Yasushi Kasa ,  Johnny Chung-Lee Chen ,  Guowei Wang ,  Tiao-Hua Kuo

IPC分类号： G06F1200

CPC分类号： G11C8/12 ,  G11C15/046 ,  G11C16/22

摘要： A simultaneous operation flash memory capable of providing double protection to An OTP sector. The preferred simultaneous operation flash memory comprises an OTP write-protect CAM, which is in a programmed state if the OTP sector is write-protected. In addition, the preferred simultaneous flash memory further includes an OTP sector lock CAM that is electrically connected with the OTP write-protect CAM. The OTP sector lock CAM is used to lock the OTP write-protect CAM in the programmed state, which, in turn, will designate the OTP sector as read only.

摘要翻译： 同时操作的闪存，能够为OTP扇区提供双重保护。 优选的同时操作闪速存储器包括OTP写保护CAM，如果OTP扇区被写保护，其处于编程状态。 此外，优选的同时闪存还包括与OTP写保护CAM电连接的OTP扇区锁CAM。 OTP扇区锁CAM用于将OTP写保护CAM锁定在编程状态，而后者又将OTP扇区指定为只读。

公开(公告)号：US06571307B1

公开(公告)日：2003-05-27

申请号：US09421758

申请日：1999-10-19

申请人： Tiao-Hua Kuo ,  Nancy S. Leong ,  Takao Akagoi ,  Yasushi Kasa

发明人： Tiao-Hua Kuo ,  Nancy S. Leong ,  Takao Akagoi ,  Yasushi Kasa

IPC分类号： G06F1300

CPC分类号： G11C16/06 ,  G11C2216/22

摘要： A multiple purpose bus for a flash memory device that allows six sets of data signals to utilize the bus. The multiple purpose bus includes sixteen circuit lines that extend from one end of the memory device to another end of the memory device. Control signals that correspond to each set of data signals couple the sets of data signals to the circuit lines. A grounding circuit is provided that couples the circuit lines to a ground when none of the sets of data signals are utilizing the multiple purpose bus.

摘要翻译： 用于闪存设备的多用途总线，允许六组数据信号利用总线。 多用途总线包括从存储器件的一端延伸到存储器件的另一端的十六条电路线。 对应于每组数据信号的控制信号将数据信号组耦合到电路线。 当没有一组数据信号正在利用多用途总线时，提供将电路线耦合到地的接地电路。

公开(公告)号：US06470414B2

公开(公告)日：2002-10-22

申请号：US09893247

申请日：2001-06-26

申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC分类号： G06F1200

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option, a bank selector encoder coupled to receive a memory partition indicator signal from the memory boundary option, and a bank selector decoder coupled to receive a bank selector code from the bank selector encoder. The decoder, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

摘要翻译： 一种用于具有灵活存储区划分架构的同步操作闪速存储器件的存储体选择器电路，包括存储器边界选项，耦合以从存储器边界选项接收存储器分区指示符信号的存储体选择器编码器，以及耦合以接收 来自银行选择器编码器的存储体选择器代码。 解码器在接收到存储器地址时输出存储体选择器输出信号，以根据选择的存储器分区边界将存储器地址指向同时操作闪速存储器件中的下部存储器组或上部存储器组。

公开(公告)号：US06331950B1

公开(公告)日：2001-12-18

申请号：US09421757

申请日：1999-10-19

申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Johnny C. Chen

发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Johnny C. Chen

IPC分类号： G11C700

CPC分类号： G11C16/22 ,  G11C16/30

摘要： An input circuit for a flash memory device is disclosed. The input circuit includes an input for receiving a voltage signal from an external source representing a digital logic signal. The input circuit further includes a pull up circuit which is coupled with the input and pulls the input to a high logic level when the input is not connected to any external source.

摘要翻译： 公开了一种用于闪速存储器件的输入电路。 输入电路包括用于从表示数字逻辑信号的外部源接收电压信号的输入端。 输入电路还包括与输入耦合的上拉电路，并且当输入未连接到任何外部源时将输入拉到高逻辑电平。

公开(公告)号：US6033955A

公开(公告)日：2000-03-07

申请号：US159023

申请日：1998-09-23

申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC分类号： G11C16/04 ,  G11C5/00 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C5/063 ,  G11C16/08 ,  G11C8/10 ,  G11C8/12

摘要： A method of forming flexibly partitioned metal line segments 10 and 12 for separate memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture comprises the steps of providing a basic metal layer 2 comprising a plurality of basic metal layer segments 2a, 2b, 2c, . . . 2j separated by a plurality of gaps 6a, 6b, 6c, . . . 6i, each of the gaps having a predefined gap interval length, and providing a metal option layer 8 comprising a plurality of metal option layer segments on the basic metal layer 2, the metal option layer segments overlapping the gaps between the basic metal layer segments but leaving one of the gaps open, to form the metal line segments for the separate memory banks.

摘要翻译： 在具有柔性库分隔结构的同时操作的闪速存储器件中形成用于单独存储体的柔性分隔的金属线段10和12的方法包括以下步骤：提供包括多个基本金属层段2a，2b的基本金属层2 ，2c，。 。 。 2j由多个间隙6a，6b，6c，...分开。 。 。 如图6i所示，每个间隙具有预定的间隙间隔长度，并且提供包括在基本金属层2上的多个金属可选层段的金属选择层8，金属选择层段与基本金属层段之间的间隙重叠，但是 留下一个间隙打开，以形成用于单独存储体的金属线段。

公开(公告)号：US06005803A

公开(公告)日：1999-12-21

申请号：US159342

申请日：1998-09-23

申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC分类号： G11C16/06 ,  G11C8/12 ,  G11C16/02 ,  G11C16/08 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A decoding circuit 54 for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder 44, a lower bank decoder 58, an upper bank decoder 56, and a plurality of flexibly partitioned conductive lines coupled between the upper and lower bank decoders 56 and 58. The flexibly partitioned conductive lines 60, 62, 64, . . . 74 provide a plurality of bank address pre-decoding bits for the X-decoder 44 to row decode the memory cells along the respective word lines in the memory array 20. The memory array 20 includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are coupled to two Y-decoders 32 and 34 which provide column decoding for the memory cells in the upper and lower memory banks.

摘要翻译： 用于具有灵活存储体分区体系结构的同时操作的非易失性存储器件的解码电路54包括X解码器44，下部存储体解码器58，上部存储体解码器56和多个柔性分隔的导线， 和下部分组解码器56和58.柔性分隔的导线60,62,64。 。 。 74提供多个用于X解码器44的存储体地址预解码位，以沿着存储器阵列20中的相应字线对存储器单元进行解码。存储器阵列20包括多个灵活分割的位线，包括第一和第二 位线段将存储器阵列分隔成上部和下部存储体。 上存储体和下存储体中的位线段耦合到两个Y解码器32和34，它们为上和下存储体中的存储单元提供列解码。

公开(公告)号：US06633949B2

公开(公告)日：2003-10-14

申请号：US09892431

申请日：2001-06-26

申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC分类号： G06F1200

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A bank selector encoder comprises a partition indicator circuit having a plurality of partition boundary indicator terminals, a plurality of inverters arranged in a plurality of columns, with each column of the inverters coupled to a respective one of a plurality of columns of ROM cells in a ROM array and a plurality of bank selector code outputs coupled to respective columns of the inverters. The partition boundary indicator terminals are capable of designating a memory partition boundary to identify an upper memory bank and a lower memory bank. The bank selector encoder is capable of generating an identifying bank selector code for each of a plurality of the predetermined memory partition boundaries. The bank selector encoder outputs code bits of a bank selector code based upon the partition boundary indicator terminals.

摘要翻译： 存储体选择器编码器包括具有多个分区边界指示符终端的分区指示器电路，多列排列的多个反相器，其中每列反相器耦合到多列ROM单元的相应一列 ROM阵列和耦合到反相器的各列的多个存储体选择器代码输出。 分区边界指示符终端能够指定存储器分区边界以识别上部存储体和下部存储体。 存储体选择器编码器能够为多个预定的存储分区边界中的每一个生成识别库选择器代码。 存储体选择器编码器基于分区边界指示符终端输出存储体选择器代码的代码位。

公开(公告)号：US06275894B1

公开(公告)日：2001-08-14

申请号：US09159489

申请日：1998-09-23

申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC分类号： G11C1604

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option 18, a bank selector encoder 2 coupled to receive a memory partition indicator signal from the memory boundary option 18, and a bank selector decoder 3 coupled to receive a bank selector code from the bank selector encoder 2. The decoder 3, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

摘要翻译： 一种用于具有灵活存储体分区架构的同步操作闪速存储器件的存储体选择器电路包括存储器边界选项18，耦合以从存储器边界选项18接收存储器分区指示符信号的存储体选择器编码器2以及存储体选择器解码器3 耦合以从存储体选择器编码器2接收存储体选择器代码。解码器3在接收到存储器地址时输出存储体选择器输出信号，以将同时操作中的存储器地址指向下存储体或较高存储体 闪存设备，根据所选择的内存分区边界。

公开(公告)号：US5995415A

公开(公告)日：1999-11-30

申请号：US159142

申请日：1998-09-23

申请人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

发明人： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC分类号： G11C16/02 ,  G11C7/18 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C7/00

CPC分类号： G11C16/08 ,  G11C7/18 ,  G11C8/12

摘要： A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array 20 including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines 28 and 30 each coupled to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder 22 coupled to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders 24 and 26 are coupled to the X-decoder 22. Two Y-decoders 32 and 34 are coupled to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.

摘要翻译： 具有柔性库分隔体系结构的同时操作的非易失性存储器件包括存储器阵列20，存储器阵列20包括布置在多个列和行中的多个存储器单元，多个位线28和30，每个位线连接到相应的列 存储器单元，每个位线包括由指定上存储体和下存储体之间的存储器分区边界的间隙分隔的第一和第二位线段，以及耦合到存储器单元的各行的X解码器22进行行解码 存储器阵列响应于接收上部和下部存储器地址。 两个预解码器24和26耦合到X解码器22.两个Y解码器32和34分别耦合到位线段以对上和下存储体中的存储单元提供列解码。

公开(公告)号：US06397313B1

公开(公告)日：2002-05-28

申请号：US09632390

申请日：2000-08-04

申请人： Yasushi Kasa ,  Guowei Wang

发明人： Yasushi Kasa ,  Guowei Wang

IPC分类号： G06F1206

CPC分类号： G11C29/781 ,  G11C2216/22

摘要： The present invention discloses sector-based redundancy that is capable of making repairs using a plurality of redundant columns of memory cells in a dual bank memory device during simultaneous operation. The simultaneous operation memory device includes a plurality of redundant blocks that can be configured to be located in an upper bank or a sliding lower bank. The redundant blocks are comprised of sectors and each sector contains columns of memory cells. During simultaneous operation, the memory device is capable of reading the columns of memory cells in one bank and writing columns of memory cells in the other bank at the same time. In addition, the simultaneous operation memory device uses sector-based redundancy to repair columns of memory cells that are defective in one bank by electrically exchanging them with redundant columns of memory cells and, at the same time, repair columns of memory cells that are defective in the other bank. The dual bank sector-based redundancy includes a plurality of address CAM circuits that are configurably associated with the redundant blocks based on the bank location of the redundant blocks. The address CAM circuits are configured by a redundancy CAM read drain decoder circuit.

摘要翻译： 本发明公开了基于扇区的冗余，其能够在同时操作期间使用双组存储器设备中的多个冗余列的存储单元进行修复。 同时操作存储装置包括多个冗余块，其可被配置为位于上层或滑动下层。 冗余块由扇区组成，每个扇区包含存储单元列。 在同步操作期间，存储器件能够读取一个存储体中的存储单元的列，并且同时在另一个存储体中写入存储单元的列。 此外，同时操作存储器件使用基于扇区的冗余来通过与存储器单元的冗余列电交换来修复存储单元中有缺陷的存储器单元的列，并且同时修复有缺陷的存储器单元的列 在另一家银行。 基于双银行扇区的冗余包括多个地址CAM电路，其基于冗余块的存储单元位置与冗余块可配置地相关联。 地址CAM电路由冗余CAM读取漏极解码器电路配置。