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公开(公告)号:US20170199786A1
公开(公告)日:2017-07-13
申请号:US15320852
申请日:2014-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Naveen Muralimanohar , Erik Ordentlich , Amit S. Sharma
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/0631 , G06F3/0679 , G06F11/1048 , G11C7/1006 , G11C8/10 , G11C29/702 , G11C29/808 , H03M13/13 , H03M13/2921 , H03M13/6566
Abstract: According to an example, a method for assigning redundancy in encoding data onto crossbar memory arrays is provided wherein each of said crossbar memory arrays include cells. The data may be allocated to a subset of the cells in multiple crossbar memory arrays. The redundancy for the data may then be assigned based on coordinates of the subset of cells within the multiple crossbar memory arrays onto which the data is allocated.
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公开(公告)号:US20160352359A1
公开(公告)日:2016-12-01
申请号:US15113903
申请日:2014-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Erik Ordentlich , Ron M. Roth
CPC classification number: H03M13/1575 , H03M13/155 , H03M13/51
Abstract: Encoding or decoding can operate a processing system to apply one or more recursive relations to a known parameter associated with a length m and a Hamming weight l to produce a computed parameter associated with length m−1. An encoding process can thus assign values to bits of a code based on comparison of the data value being encoded and the computed parameter. A decoding process can use the computed parameters in a calculation of a decoded data value.
Abstract translation: 编码或解码可以操作处理系统以将一个或多个递归关系应用于与长度m和汉明权重1相关联的已知参数,以产生与长度m-1相关联的计算参数。 因此,编码处理可以基于正在编码的数据值与所计算的参数的比较来将值分配给代码的位。 在解码数据值的计算中,解码处理可以使用计算出的参数。
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公开(公告)号:US20160343432A1
公开(公告)日:2016-11-24
申请号:US15113914
申请日:2014-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Richard H. Henze , Naveen Muralimanohar , Yoocharn Jeon , Martin Foltin , Erik Ordentlich , Gregg B. Lesartre , R. Stanley Williams
IPC: G11C13/00 , H01L27/24 , H01L45/00 , H01L23/528
CPC classification number: G11C13/004 , G11C5/025 , G11C11/005 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L23/528 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.
Abstract translation: 具有多个延迟层的非易失性存储器件包括至少两个交叉存储器阵列,每个横向存储器阵列包括多个存储器单元,每个存储器单元连接到字线和位于交叉点的位线。 交叉开关存储器阵列每个具有不同的延迟。 交叉开关存储器阵列形成在单个管芯上。
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