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    CONVOLUTION ACCELERATORS
    21.
    发明申请
    CONVOLUTION ACCELERATORS 审中-公开

    公开(公告)号：US20180373674A1

    公开(公告)日：2018-12-27

    申请号：US16052507

    申请日：2018-08-01

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Miao Hu ,  John Paul Strachan ,  Naveen Muralimanohar

    IPC: G06F17/14 ,  G06F17/15

    Abstract: Examples herein relate to convolution accelerators. An example convolution accelerator may include a transformation crossbar array programmed to calculate a Fourier Transformation of a first vector with a transformation matrix and a Fourier Transformation of a second vector with the transformation matrix. A circuit of the example convolution accelerator may multiply the Fourier Transformation of the first vector with the Fourier Transformation of the second vector to calculate a product vector. The example convolution accelerator may have an inverse transformation crossbar array programmed to calculate an Inverse Fourier Transformation of the product vector according to an inverse transformation matrix.

    ANALOG MULTIPLIER-ACCUMULATORS
    22.
    发明申请
    ANALOG MULTIPLIER-ACCUMULATORS 审中-公开

    公开(公告)号：US20180253643A1

    公开(公告)日：2018-09-06

    申请号：US15449071

    申请日：2017-03-03

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Brent Buchanan ,  Miao Hu ,  John Paul Strachan

    IPC: G06N3/063 ,  G11C13/00 ,  H03M1/12

    CPC classification number: G06N3/0635 ,  G06F7/5443 ,  G06F2207/4802 ,  G06F2207/4824 ,  G11C13/0069 ,  H03M1/1245

    Abstract: An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line. The integration control signal may be to close the switch for a specified amount of time during each of the plurality of time periods.

    NONVOLATILE MEMORY CROSS-BAR ARRAY
    24.
    发明申请
    NONVOLATILE MEMORY CROSS-BAR ARRAY 审中-公开

    公开(公告)号：US20170358352A1

    公开(公告)日：2017-12-14

    申请号：US15535765

    申请日：2014-12-15

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G06G7/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/79

    Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

    Analog multiplier-accumulators
    26.
    发明授权
    Analog multiplier-accumulators 有权

    公开(公告)号：US11315009B2

    公开(公告)日：2022-04-26

    申请号：US15449071

    申请日：2017-03-03

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Brent Buchanan ,  Miao Hu ,  John Paul Strachan

    IPC: G06N3/063 ,  G11C13/00 ,  H03M1/12 ,  G06F7/544

    Abstract: An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line. The integration control signal may be to close the switch for a specified amount of time during each of the plurality of time periods.

    Linear transformation accelerators
    28.
    发明授权
    Linear transformation accelerators 有权

    公开(公告)号：US10529418B2

    公开(公告)日：2020-01-07

    申请号：US16079998

    申请日：2016-02-19

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Miao Hu ,  John Paul Strachan ,  Zhiyong Li ,  R. Stanley Williams

    IPC: G11C13/00 ,  G11C11/56

    Abstract: Examples herein relate to linear transformation accelerators. An example linear transformation accelerator may include a crossbar array programmed to calculate a linear transformation. The crossbar array has a plurality of words lines, a plurality of bit lines, and a memory cell coupled between each unique combination of one word line and one bit line, where the memory cells are programmed according to a linear transformation matrix. The plurality of word lines are to receive an input vector, and the plurality of bit lines are to output an output vector representing a linear transformation of the input vector.

    Nonvolatile memory cross-bar array
    30.
    发明授权
    Nonvolatile memory cross-bar array 有权

    公开(公告)号：US10181349B2

    公开(公告)日：2019-01-15

    申请号：US15535765

    申请日：2014-12-15

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

    IPC: G11C13/00 ,  G06G7/16

    Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

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