公开(公告)号：US20080162897A1

公开(公告)日：2008-07-03

申请号：US11872846

申请日：2007-10-16

申请人： Tobias Gemmeke ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jochen Preiss

IPC分类号： G06F9/305

CPC分类号： H03K19/20 ,  G06F7/00 ,  G06F9/30029

摘要： A binary logic unit to apply any Boolean operation on two input signals (va, vb) is described, wherein any Boolean operation to be applied on the input signals (va, vb) is defined by a particular combination of well defined control signals (ctl0, ctl1, ctl2, ctl3), wherein the input signals (va, vb) are used to select a control signal (ctl0, ctl1, ctl2, ctl3) as an output signal (vo) of the binary logic unit representing the result of a particular Boolean operation applied on the two input signals (va, vb). Furthermore a method to operate such a binary logic unit is described.

摘要翻译： 描述了用于对两个输入信号（v SUB，a，B）进行任何布尔运算的二进制逻辑单元，其中应用于输入信号的任何布尔运算（v 由定义良好的控制信号（ct10，ct11，ct12，ct13）的特定组合定义，其中输入信号（v 用于选择作为输出信号的控制信号（ct1 0，ct1，ctl2，ct13）作为输出信号（v < / SUB>）表示施加在两个输入信号（v SUB a，v B b）上的特定布尔运算的结果的二进制逻辑单元。 此外，描述了操作这种二进制逻辑单元的方法。

公开(公告)号：US08312069B2

公开(公告)日：2012-11-13

申请号：US11872811

申请日：2007-10-16

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Dieter Wendel

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Dieter Wendel

IPC分类号： G06F7/00

CPC分类号： G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

摘要： A permute unit includes permute logic and a crossbar working in cycles defined by clocking signals and generates one valid output vector per cycle by treating two parallel input vectors per cycle. The permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals. In the first inner cycle, first halves of both input vectors are treated. In the second inner cycle, second halves of both input vectors are treated and a valid output vector is generated from the results of the treatments within the first and the second inner cycles.

摘要翻译： 置换单元包括置换逻辑和交叉开关，其周期由定时信号定义，并且通过每个周期处理两个并行输入向量来产生每个周期的一个有效输出向量。 置换单元通过每个外部周期执行两个内部循环由时钟信号定义来进行双重泵浦。 在第一个内循环中，处理两个输入向量的前半部分。 在第二内循环中，处理两个输入向量的第二半，并且从第一和第二内循环中的处理结果生成有效的输出向量。

公开(公告)号：US08452824B2

公开(公告)日：2013-05-28

申请号：US11872846

申请日：2007-10-16

申请人： Tobias Gemmeke ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jochen Preiss

IPC分类号： G06F15/00

CPC分类号： H03K19/20 ,  G06F7/00 ,  G06F9/30029

摘要： A binary logic unit to apply any Boolean operation on two input signals (va, vb) is described, wherein any Boolean operation to be applied on the input signals (va, vb) is defined by a particular combination of well defined control signals (ctl0, ctl1, ctl2, ctl3), wherein the input signals (va, vb) are used to select a control signal (ctl0, ctl1, ctl2, ctl3) as an output signal (vo) of the binary logic unit representing the result of a particular Boolean operation applied on the two input signals (va, vb). Furthermore a method to operate such a binary logic unit is described.

摘要翻译： 描述了对两个输入信号（va，vb）应用任何布尔运算的二进制逻辑单元，其中要施加到输入信号（va，vb）上的任何布尔运算由明确定​​义的控制信号（ct10 ，ctl1，ctl2，ctl3），其中输入信号（va，vb）用于选择控制信号（ctl0，ctl1，ctl2，ctl3）作为代表a的结果的二进制逻辑单元的输出信号（vo） 特定的布尔运算应用于两个输入信号（va，vb）。 此外，描述了操作这种二进制逻辑单元的方法。

公开(公告)号：US07795914B2

公开(公告)日：2010-09-14

申请号：US12262255

申请日：2008-10-31

申请人： Tobias Gemmeke ,  Friedrich Schroeder ,  Stefan Bonsels ,  Dieter Wendel

发明人： Tobias Gemmeke ,  Friedrich Schroeder ,  Stefan Bonsels ,  Dieter Wendel

IPC分类号： H03K19/00 ,  H03K19/02

CPC分类号： H03K19/09429 ,  H03K19/0016

摘要： A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage. The three stage circuit is switched to a low leakage state by a control signal feed via the control input and setting the two transistors in their off state resulting in a second stage with a floating common output filtered by the third stage via the control signal actively driven the data output to a specific logic value.

摘要翻译： 根据本发明的三级电路包括数据输入，数据输出，控制输入，两个电压输入。 第一级电连接到数据输入和控制输入，并由具有两个输出的组合电路定义。 第二级由两个电压源输入之间串联连接的至少两个晶体管形成，它们的输入电连接到第一级的相应输出，并具有共同的输出，使得与第一级连接时，它们以三 状态门 该三级电路的第三级电连接到第二级的控制输入和公共输出端。 三级电路经由控制输入端通过控制信号馈电切换到低泄漏状态，并将两个晶体管设置为关闭状态，从而产生第二级，其中第一级通过主动驱动的控制信号由第三级滤波的浮动公共输出 数据输出到一个特定的逻辑值。

公开(公告)号：US20090115504A1

公开(公告)日：2009-05-07

申请号：US12262255

申请日：2008-10-31

申请人： Tobias Gemmeke ,  Friedrich Schroeder ,  Stefan Bonsels ,  Dieter Wendel

发明人： Tobias Gemmeke ,  Friedrich Schroeder ,  Stefan Bonsels ,  Dieter Wendel

IPC分类号： H01L25/00

CPC分类号： H03K19/09429 ,  H03K19/0016

摘要： A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage. The three stage circuit is switched to a low leakage state by a control signal feed via the control input and setting the two transistors in their off state resulting in a second stage with a floating common output filtered by the third stage via the control signal actively driven the data output to a specific logic value.

摘要翻译： 根据本发明的三级电路包括数据输入，数据输出，控制输入，两个电压输入。 第一级电连接到数据输入和控制输入，并由具有两个输出的组合电路定义。 第二级由两个电压源输入之间串联连接的至少两个晶体管形成，它们的输入电连接到第一级的相应输出，并具有共同的输出，使得与第一级连接时，它们以三 状态门 该三级电路的第三级电连接到第二级的控制输入和公共输出端。 三级电路经由控制输入端通过控制信号馈电切换到低泄漏状态，并将两个晶体管设置为关闭状态，从而产生第二级，其中第一级通过主动驱动的控制信号由第三级滤波的浮动公共输出 数据输出到一个特定的逻辑值。

公开(公告)号：US07639046B2

公开(公告)日：2009-12-29

申请号：US11850736

申请日：2007-09-06

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

IPC分类号： H03K19/00 ,  H03K17/16 ,  H03K19/003 ,  G06F1/00 ,  G05F1/10 ,  G05F3/02

CPC分类号： H03K19/0016

摘要： A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.

摘要翻译： 一种降低时钟门控同步电路内的功耗的方法，所述同步电路包括至少两个连续的级，其中每个阶段如果被激活，则将周期性的数据信号周期传播到后一级，包括以下步骤：导出本地时钟激活 来自外部时钟激活信号的信号，其中所述本地时钟激活信号每周期改变其值，外部时钟激活信号指示传播，数据信号和本地时钟激活信号从一个特定阶段到后一个周期循环传播 每当通过从时钟激活信号导出或通过传播通过同步电路在特定阶段的本地时钟激活信号在两个连续周期之间改变其值时，为了在同一时钟域内传播数据信号和本地时钟激活信号 通过时钟门控同步电路。

公开(公告)号：US20090135961A1

公开(公告)日：2009-05-28

申请号：US12273985

申请日：2008-11-19

申请人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

发明人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

IPC分类号： H04L27/06

CPC分类号： G01R31/318536

摘要： System and Method for Scanning Sequential Logic Elements A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.

摘要翻译： 用于扫描顺序逻辑元件的系统和方法公开了用于扫描顺序逻辑元件的数字系统和方法。 数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。 至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。 可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

公开(公告)号：US20080276140A1

公开(公告)日：2008-11-06

申请号：US12042944

申请日：2008-03-05

申请人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318575

摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

摘要翻译： 分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。 至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。 对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择 。

公开(公告)号：US20080169842A1

公开(公告)日：2008-07-17

申请号：US11850745

申请日：2007-09-06

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.

摘要翻译： 一种用于降低时钟门控同步电路内的功耗的设计结构，所述同步电路包括至少两个连续级，其中每个级如果被激活，则逐周期地将数据信号周期传播到后级，所述两个连续级包括至少一个控制寄存器 ，数据寄存器和本地时钟缓冲器（LCB），其中每个级如果被激活，则将周期内存储的数据信号周期传播到后级的数据寄存器。

公开(公告)号：US20080169841A1

公开(公告)日：2008-07-17

申请号：US11850736

申请日：2007-09-06

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.

摘要翻译： 一种降低时钟门控同步电路内的功耗的方法，所述同步电路包括至少两个连续的级，其中每个阶段如果被激活，则将周期性的数据信号周期传播到后一级，包括以下步骤：导出本地时钟激活 来自外部时钟激活信号的信号，其中所述本地时钟激活信号每周期改变其值，外部时钟激活信号指示传播，数据信号和本地时钟激活信号从一个特定阶段到后一个周期循环传播 每当通过从时钟激活信号导出或通过传播通过同步电路在特定阶段的本地时钟激活信号在两个连续周期之间改变其值时，为了在同一时钟域内传播数据信号和本地时钟激活信号 通过时钟门控同步电路。