公开(公告)号：US20070013685A1

公开(公告)日：2007-01-18

申请号：US11270694

申请日：2005-11-10

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa

IPC分类号： G09G5/00

CPC分类号： G09G3/2007 ,  G09G2310/027 ,  G09G2360/18

摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects VSSL for supplying a first power supply voltage VSS to memory cells MC are formed in a metal interconnect layer in which a plurality of wordlines WL are formed; and wherein a plurality of second power supply interconnects VDDL for supplying a second power supply voltage VDD to the memory cells are formed in another metal interconnect layer in which a plurality of bitlines BL are formed, the second power supply voltage VDD being higher than the first power supply voltage VSS. A plurality of bitline protection interconnects SHD are formed in a layer above the bitlines BL, and each of the bitline protection interconnects SHD at least partially covers one of the bitlines BL in a plan view. A third power supply interconnect GL for supplying a third power supply voltage to circuits other than the display memory are formed in a layer above the bitline protection interconnects SHD, the third power supply voltage being higher than the second power supply voltage VDD.

摘要翻译： 一种具有显示存储器的集成电路器件，其中在形成有多个字线WL的金属互连层中形成有用于向存储单元MC提供第一电源电压VSS的多个第一电源互连VSSL; 并且其中，在形成有多个位线BL的另一个金属互连层中形成有用于将第二电源电压VDD提供给存储单元的多个第二电源互连VDDL，第二电源电压VDD高于第一电源电压VDD 电源电压VSS。 多个位线保护互连SHD形成在位线BL上方的层中，并且每个位线保护互连SHD在平面图中至少部分地覆盖位线BL之一。 用于将第三电源电压提供给除了显示存储器之外的电路的第三电源互连GL形成在位线保护互连SHD上方的层中，第三电源电压高于第二电源电压VDD。

公开(公告)号：US20070013074A1

公开(公告)日：2007-01-18

申请号：US11270586

申请日：2005-11-10

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa

IPC分类号： H01L23/52

CPC分类号： H01L23/552 ,  G11C5/063 ,  H01L24/49 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01066 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2224/45099

摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.

摘要翻译： 一种具有显示存储器的集成电路器件，其中在形成多个位线的金属互连层中提供用于向多个存储单元提供第一电源电压的多个第一电源互连件; 其中在形成有多个字线的金属互连层中提供用于向所述存储单元提供第二电源电压的第二电源互连，所述第二电源电压高于所述第一电源电压; 其中多个位线保护互连形成在所述位线上方的层中，所述位线保护互连中的每一个在平面图中至少部分地覆盖所述位线之一; 并且其中，用于将第三电源电压提供给除了所述显示存储器之外的所述集成电路装置的电路的第三电源互连设置在所述位线保护互连线上方的层中，所述第三电源电压高于所述第二电源电压 。

公开(公告)号：US20070002670A1

公开(公告)日：2007-01-04

申请号：US11270549

申请日：2005-11-10

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

IPC分类号： G11C8/00

CPC分类号： G09G3/3685 ,  G09G3/20 ,  G09G3/3611 ,  G09G5/39 ,  G09G5/395 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0278 ,  G09G2360/12

摘要： An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.

摘要翻译： 一种具有显示存储器的集成电路装置，该显示存储器从显示在具有多个扫描线和多条数据线的显示面板中的图像信息中存储至少一帧的数据，所述显示存储器包括多个字线，多个 位线，多个存储单元和字线控制电路; 并且字线控制电路在显示面板的一个水平扫描周期中从字线中选择相同的字线N次（N是大于1的整数）。

公开(公告)号：US20070002509A1

公开(公告)日：2007-01-04

申请号：US11477720

申请日：2006-06-30

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

IPC分类号： H02H9/00

CPC分类号： G09G3/3688 ,  G02F1/13452 ,  G02F2202/28 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/027

摘要： An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

摘要翻译： 集成电路器件包括形成在矩形区域中并与焊盘PDx电连接的焊盘PDx和静电放电保护元件ESDx。 垫PDx设置在静电放电保护元件ESDx的上层中，使得焊盘的布置方向平行于形成有静电放电保护元件ESDx的区域的长边方向，并且焊盘PDx重叠 部分或全部静电放电保护元件ESDx。

公开(公告)号：US20070001973A1

公开(公告)日：2007-01-04

申请号：US11270632

申请日：2005-11-10

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Katsuhiko Maki

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Katsuhiko Maki

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2360/18

摘要： An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a logic circuit block LB, a grayscale voltage generation circuit block GB, data driver blocks DB1 to DB4, and a power supply circuit block PB. The data driver blocks DB1 to DB4 are disposed between the logic circuit block LB and the grayscale voltage generation circuit block GB, and the power supply circuit block PB.

摘要翻译： 一种集成电路装置，包括沿着第一方向D 1布置的第一至第N电路块CB 1至CBN，当第一方向D 1是从集成电路器件的第一侧朝向与第一方向相反的第三侧的方向时 所述第一侧为短边，当第二方向D 2为从所述集成电路器件的第二侧朝向与所述第二侧相反的第四侧的方向时，所述第二侧为长边。 电路块CB 1至CBN包括逻辑电路块LB，灰度电压产生电路块GB，数据驱动器块DB 1至DB 4和电源电路块PB。 数据驱动器块DB 1至DB 4设置在逻辑电路块LB和灰度级电压产生电路块GB之间，以及电源电路块PB。

公开(公告)号：US20070001969A1

公开(公告)日：2007-01-04

申请号：US11270552

申请日：2005-11-10

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2310/027

摘要： An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines. The display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines WL, a plurality of bitlines BL, a plurality of memory cells MC, and a data read control circuit. Each of the RAM blocks is disposed along a first direction X in which the bitlines BL extend. The data read control circuit controls data reading so that data for pixels corresponding to the signal lines is read out by N times reading in one horizontal scan period 1H of the display panel (N is an integer larger than 1)

摘要翻译： 集成电路装置具有显示存储器，其存储显示在具有多条扫描线和多条数据线的显示面板中的至少一帧的数据。 显示存储器包括多个RAM块，每个RAM块包括多个字线WL，多个位线BL，多个存储单元MC和数据读取控制电路。 每个RAM块沿着位线BL延伸的第一方向X设置。 数据读取控制电路控制数据读取，使得对应于信号线的像素的数据在显示面板的一个水平扫描周期1H（N是大于1的整数）中读出N次读数，

公开(公告)号：US20060010099A1

公开(公告)日：2006-01-12

申请号：US11171493

申请日：2005-06-30

申请人： Naoko Takeda ,  Kissei Matsumoto ,  Takashi Kumagai ,  Toshihide Ooba ,  Hiroshi Iwata ,  Shingo Yamade

发明人： Naoko Takeda ,  Kissei Matsumoto ,  Takashi Kumagai ,  Toshihide Ooba ,  Hiroshi Iwata ,  Shingo Yamade

IPC分类号： G06F17/30

CPC分类号： G06F3/0482 ,  G06F3/04892

摘要： To provide a reproduction apparatus able to easily select a desired content data based on an attribute of the content data by a simple operation from a user and a reproduction method for the same, wherein the reproduction apparatus having: a display displaying the item; a first operation unit instructing a switch of the attribute; a second function unit instructing a selection of a predetermined item on the display; and a processing unit switching a first screen from a screen of a plurality of items so as to display a plurality of items when the first operation key is operated, and switching to a second screen displaying a plurality of item when the second operation key is operated when a plurality of item is displayed on the first screen.

摘要翻译： 为了提供能够通过用户的简单操作基于内容数据的属性容易地选择期望的内容数据的再现设备及其再现方法，其中所述再现设备具有：显示该项目的显示; 第一操作单元，指示所述属性的切换; 指示在显示器上选择预定项目的第二功能单元; 以及处理单元，从多个项目的屏幕切换第一屏幕，以便当第一操作键被操作时显示多个项目，并且当第二操作键被操作时切换到显示多个项目的第二屏幕 当在第一屏幕上显示多个项目时。

公开(公告)号：US06534864B1

公开(公告)日：2003-03-18

申请号：US09428821

申请日：1999-10-28

申请人： Kazuo Tanaka ,  Takashi Kumagai ,  Junichi Karasawa ,  Kunio Watanabe

发明人： Kazuo Tanaka ,  Takashi Kumagai ,  Junichi Karasawa ,  Kunio Watanabe

IPC分类号： H01L2348

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： A semiconductor memory device (SRAM) comprises memory cells, each of which includes two load transistors, two driver transistors and two transfer transistors. The SRAM cell includes a semiconductor substrate in which the transistors are formed, a first interlayer dielectric formed on the semiconductor substrate, first contact portions formed in the first interlayer dielectric and first wiring layers (node wiring layers and pad layers) formed on the first interlayer dielectric. The first contact portions and the first wiring layers include metal layers made of refractory metal and a refractory metal nitride layers. This semiconductor memory device of the present invention is capable of enhancing an integration degree of wiring layers and achieving a microfabrication.

摘要翻译： 半导体存储器件（SRAM）包括存储单元，每个存储单元包括两个负载晶体管，两个驱动晶体管和两个转移晶体管。 SRAM单元包括其中形成晶体管的半导体衬底，形成在半导体衬底上的第一层间电介质，形成在第一层间电介质中的第一接触部分和形成在第一层间电介质上的第一布线层（节点布线层和衬垫层） 电介质。 第一接触部分和第一布线层包括由难熔金属制成的金属层和难熔金属氮化物层。 本发明的半导体存储器件能够提高布线层的集成度并实现微细加工。

公开(公告)号：US06232670B1

公开(公告)日：2001-05-15

申请号：US09361043

申请日：1999-07-26

申请人： Takashi Kumagai ,  Junichi Karasawa ,  Kazuo Tanaka ,  Kunio Watanabe

发明人： Takashi Kumagai ,  Junichi Karasawa ,  Kazuo Tanaka ,  Kunio Watanabe

IPC分类号： H01L2711

CPC分类号： H01L27/1104

摘要： First and second memory cells of an SRAM comprises first, second, and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer diverges from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The pattern of the first, second, and third conductive layers of the second memory cell is a rotated pattern of the first, second, and third conductive layers in the first memory cell at an angle of 180 degrees around an axis perpendicular to the main surface of a semiconductor substrate.

摘要翻译： SRAM的第一和第二存储单元包括第一，第二和第三导电层。 第一导电层是用于第一负载晶体管和第一驱动晶体管的栅电极。 第二导电层从场氧化物区域上的第一导电层发散，并且电连接到第二驱动器晶体管有源区。 第三导电层是用于第二负载晶体管的栅电极和第二驱动晶体管。 第三导电层电连接到第一负载晶体管有源区。 第二存储单元的第一，第二和第三导电层的图案是第一存储单元中的第一，第二和第三导电层的旋转图案，围绕垂直于主表面的轴以180度的角度 的半导体衬底。

公开(公告)号：US06181071B2

公开(公告)日：2001-01-30

申请号：US09031609

申请日：1998-02-27

申请人： Akimasa Yuuki ,  Mitsumasa Umesaki ,  Sadayuki Matsumoto ,  Takashi Kumagai ,  Shin Kawabe

发明人： Akimasa Yuuki ,  Mitsumasa Umesaki ,  Sadayuki Matsumoto ,  Takashi Kumagai ,  Shin Kawabe

IPC分类号： G02F1335

CPC分类号： G02F1/133615

摘要： A display panel with a reduced capacitive coupling. The panel includes a transmission type liquid crystal panel. A lamp is provided adjacent at least one side of a light guide plate to guide the light to the crystal panel. A high frequency current supply is used to power the light. A reflective plate encircles the lamp so as to introduce the light to the light guide plate. A housing is made of a thin metal plate. Each portion of the housing is connected with a common electrical potential. Part of the housing extends away from the reflective plate around the lamp or contains an opening in the same location. By this arrangement, the capacitance between the reflective plate and the housing is made smaller thus reducing the leakage current.

摘要翻译： 具有降低电容耦合的显示面板。 面板包括透射型液晶面板。 在导光板的至少一侧附近设置灯以将光引导到晶体面板。 使用高频电流源供电。 反射板围绕灯，以将光引入导光板。 外壳由薄金属板制成。 壳体的每个部分与公共电位相连。 壳体的一部分远离灯的反射板延伸，或者在相同位置处包含开口。 通过这种布置，使反射板和壳体之间的电容变小，从而减小漏电流。