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    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device
    21.
    发明申请
    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device 审中-公开
    包括具有低位错缺陷密度的外延层的多层结构以及包含该外延层的半导体器件以及制造该半导体器件的方法

    公开(公告)号：US20050274981A1

    公开(公告)日：2005-12-15

    申请号：US11194529

    申请日：2005-08-02

    申请人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    发明人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    IPC分类号： H01L21/20 ,  H01L21/8238 ,  H01L31/072 ,  H01L31/117

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

    摘要： A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

    摘要翻译： 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

    Method of fabricating MOS transistor using total gate silicidation process
    22.
    发明申请
    Method of fabricating MOS transistor using total gate silicidation process 失效
    使用全栅极硅化工艺制造MOS晶体管的方法

    公开(公告)号：US20050009265A1

    公开(公告)日：2005-01-13

    申请号：US10806301

    申请日：2004-03-22

    申请人： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

    发明人： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/84

    CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/66545

    摘要： There is provided a method of fabricating a MOS transistor using a total gate silicidation process. The method includes forming an insulated gate pattern on a semiconductor substrate. The insulated gate pattern includes a silicon pattern and a sacrificial layer pattern, which are sequentially stacked. Spacers covering sidewalls of the gate pattern are formed, and source/drain regions are formed by injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks. The silicon pattern is exposed by removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions. The exposed silicon pattern is fully converted into a gate silicide layer, and concurrently a source/drain silicide layer is selectively formed on the surface of the source/drain regions.

    摘要翻译： 提供了使用总栅极硅化工艺制造MOS晶体管的方法。 该方法包括在半导体衬底上形成绝缘栅极图案。 绝缘栅图案包括依次层叠的硅图案和牺牲层图案。 形成覆盖栅极图案的侧壁的间隔物，并且通过使用间隔物和栅极图案作为离子注入掩模将杂质离子注入到半导体衬底中来形成源极/漏极区域。 通过去除具有源极/漏极区域的半导体衬底上的牺牲层图案来暴露硅图案。 暴露的硅图案完全转换为栅极硅化物层，并且同时在源极/漏极区域的表面上选择性地形成源极/漏极硅化物层。

    Semiconductor devices having faceted channels and methods of fabricating such devices
    23.
    发明授权
    Semiconductor devices having faceted channels and methods of fabricating such devices 有权
    具有小平面通道的半导体器件和制造这种器件的方法

    公开(公告)号：US07671420B2

    公开(公告)日：2010-03-02

    申请号：US11281599

    申请日：2005-11-18

    申请人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

    发明人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

    IPC分类号： H01L29/76 ,  H01L27/148 ,  H01L27/01

    CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

    摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.

    摘要翻译： 公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。 表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。 根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

    Transistors having reinforcement layer patterns and methods of forming the same
    26.
    发明授权
    Transistors having reinforcement layer patterns and methods of forming the same 有权
    具有加强层图案的晶体管及其形成方法

    公开(公告)号：US07307274B2

    公开(公告)日：2007-12-11

    申请号：US11204564

    申请日：2005-08-15

    申请人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

    发明人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

    IPC分类号： H01L29/06

    CPC分类号： H01L29/66628 ,  H01L21/26586 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7834

    摘要： According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To the end, at least one gate pattern is disposed on an active region of a semiconductor substrate. Reinforcement layer patterns are formed to extend respectively from sidewalls of the gate pattern and disposed on a main surface of the semiconductor substrate. Each reinforcement layer pattern partially exposes each sidewall of the gate pattern. Impurity regions are disposed in the reinforcement layer patterns and the active region of the semiconductor substrate and overlap the gate pattern. Spacer patterns are disposed on the reinforcement layer patterns and partially cover the sidewalls of the gate pattern.

    摘要翻译： 根据本发明的一些实施例，提供了包括具有加强层图案的晶体管和其形成方法的线光掩模。 晶体管和方法提供了在半导体制造工艺期间补偿部分去除量的应变硅层的方法。 最后，在半导体衬底的有源区上设置至少一个栅极图案。 加强层图案分别形成为从栅极图案的侧壁延伸并设置在半导体衬底的主表面上。 每个加强层图案部分地暴露栅极图案的每个侧壁。 杂质区域设置在加强层图案和半导体衬底的有源区域中并与栅极图案重叠。 间隔图案设置在加强层图案上并且部分覆盖栅极图案的侧壁。

    Semiconductor devices having faceted channels and methods of fabricating such devices
    27.
    发明申请
    Semiconductor devices having faceted channels and methods of fabricating such devices 有权
    具有小平面通道的半导体器件和制造这种器件的方法

    公开(公告)号：US20060148154A1

    公开(公告)日：2006-07-06

    申请号：US11281599

    申请日：2005-11-18

    申请人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

    发明人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

    摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.

    摘要翻译： 公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。 表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。 根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device
    28.
    发明授权
    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device 有权
    包括具有低位错缺陷密度的外延层的多层结构以及包含该外延层的半导体器件以及制造该半导体器件的方法

    公开(公告)号：US06987310B2

    公开(公告)日：2006-01-17

    申请号：US10851336

    申请日：2004-05-24

    申请人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    发明人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    IPC分类号： H01L31/328 ,  H01L31/72 ,  H01L31/336 ,  H01L31/109 ,  H01L39/60

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

    摘要： A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

    摘要翻译： 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

    Method of fabricating MOS transistor having epitaxial region
    29.
    发明申请
    Method of fabricating MOS transistor having epitaxial region 有权
    制造具有外延区域的MOS晶体管的方法

    公开(公告)号：US20070054457A1

    公开(公告)日：2007-03-08

    申请号：US11517246

    申请日：2006-09-08

    申请人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee

    发明人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

    摘要： Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects. The method of manufacturing a MOS transistor having an epitaxial region may include forming a gate pattern on a semiconductor substrate, forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask, forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask and partially etching a lower portion of sidewalls of the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.

    摘要翻译： 示例实施例涉及制造半导体器件的方法。 其他示例实施例涉及制造具有设置在栅极图案的侧壁的下部中的外延区域的金属氧化物半导体（MOS）晶体管的方法。 提供一种制造具有提高外延生长速率并且可能具有较少缺陷的外延区域的MOS晶体管的方法。 制造具有外延区域的MOS晶体管的方法可以包括在半导体衬底上形成栅极图案，通过使用栅极图案作为离子注入，将第一杂质离子注入到半导体衬底中，形成具有第一损伤分布的第一离子注入区域 通过使用所述栅极图案作为离子注入掩模将所述第二杂质离子注入到所述半导体衬底中，形成具有与所述第一损伤分布相邻的第二损伤分布的第二离子注入区，并部分地蚀刻所述栅极图案的侧壁的下部;以及 在蚀刻的半导体衬底上原位形成外延区域。

    Semiconductor device including field effect transistor and method of forming the same
    30.
    发明授权
    Semiconductor device including field effect transistor and method of forming the same 有权
    包括场效晶体管的半导体器件及其形成方法

    公开(公告)号：US07791146B2

    公开(公告)日：2010-09-07

    申请号：US11857157

    申请日：2007-09-18

    申请人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Ji-Hye Yi

    发明人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Ji-Hye Yi

    IPC分类号： H01L29/76

    CPC分类号： H01L29/665 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.

    摘要翻译： 半导体器件包括栅极绝缘体和堆叠在衬底上的栅电极，源极/漏极图案填充形成在与栅电极相邻的相对侧的凹陷区域，源极/漏极图案由掺杂有掺杂剂的硅 - 锗构成 和设置在源极/漏极图案上的金属锗硅化物层。 金属锗硅化物层电连接到源极/漏极图案。 此外，与锗源锗排出图案中的锗量和硅量之和的锗量相比，锗量与金锗烷硅化物层中的锗量和硅量之和的比例低。