公开(公告)号：US20100156453A1

公开(公告)日：2010-06-24

申请号：US12715739

申请日：2010-03-02

申请人： Yih-Yuh Doong ,  Keh-Jeng Chang ,  Yuh-Jier Mii ,  Sally Liu ,  Lien Jung Hung ,  Victor Chih Yuan Chang

发明人： Yih-Yuh Doong ,  Keh-Jeng Chang ,  Yuh-Jier Mii ,  Sally Liu ,  Lien Jung Hung ,  Victor Chih Yuan Chang

IPC分类号： G01R31/26 ,  G01R27/26

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.

摘要翻译： 提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。 通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。 电容是在必须测量的接触或电容的目标测试结构上测量的。 然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。 通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

公开(公告)号：US20080140363A1

公开(公告)日：2008-06-12

申请号：US11638303

申请日：2006-12-12

申请人： Chung-Kai Lin ,  Cheng Hsiao ,  Sally Liu

发明人： Chung-Kai Lin ,  Cheng Hsiao ,  Sally Liu

IPC分类号： G06F17/18 ,  G06F17/50

CPC分类号： G01R31/318357 ,  G01R31/3008 ,  G01R31/318314

摘要： A method of developing a statistical model for integrated circuits includes providing a set of test patterns; collecting a set of intra-die data from the set of test patterns; collecting a set of inter-die data from the set of test patterns; generating a total variation sigma (sigma_total) from the set of intra-die data and the set of inter-die data; appointing one of a global variation sigma (sigma_global) and a local variation sigma (sigma_local) as a first sigma, and a remaining one as a second sigma; generating the first sigma from one of the set of intra-data and the set of inter-data; generating the second sigma by removing the first sigma from the sigma_total; generating a corner model for global variations based on sigma_global and the set of inter-die data; and generating a corner model for local variations based on sigma_local and the set of intra-die data.

摘要翻译： 开发用于集成电路的统计模型的方法包括提供一组测试图案; 从所述一组测试图案中收集一组模内数据; 从所述一组测试图案中收集一组晶片间数据; 从所述管芯内数据集合和所述管芯间数据集合产生总变化Σ（sigma_total）; 任命一个全球变异西格玛（sigma_global）和一个局部变异西格玛（sigma_local）作为第一个西格玛，剩下的一个作为第二西格玛; 从所述一组内部数据和所述一组数据中的一个生成所述第一西格玛; 通过从sigma_total去除第一个sigma来产生第二个sigma; 生成基于sigma_global和集合的管芯间数据的全局变化的角模型; 并且基于sigma_local和一组模内数据生成用于局部变化的角模型。

公开(公告)号：US20070294630A1

公开(公告)日：2007-12-20

申请号：US11424298

申请日：2006-06-15

申请人： Richard J. Duncan ,  Neils van Dongen ,  Constance A. Missimer ,  Sally Liu ,  Khalil Jabrane

发明人： Richard J. Duncan ,  Neils van Dongen ,  Constance A. Missimer ,  Sally Liu ,  Khalil Jabrane

IPC分类号： G06F3/00

CPC分类号： G06F3/0481 ,  G06F17/24 ,  G06Q10/107

摘要： Systems and methods for capturing content and performing operations associated with the content are described. A stylus or other pointing device may be used designate content to be captured. After content is designated, a new window is generated that includes the designated content and user interface elements for annotating, conveying or otherwise acting upon the designated content.

摘要翻译： 描述用于捕获内容并执行与内容相关联的操作的系统和方法。 可以使用触笔或其他指示装置来指定要捕获的内容。 在指定内容之后，生成包括指定内容和用户界面元素的新窗口，用于注释，传达或以其他方式对指定内容进行操作。

公开(公告)号：US08350586B2

公开(公告)日：2013-01-08

申请号：US12496946

申请日：2009-07-02

申请人： Shu-Ying Cho ,  Jiun-Kai Huang ,  Wen-Sheh Huang ,  Sally Liu

发明人： Shu-Ying Cho ,  Jiun-Kai Huang ,  Wen-Sheh Huang ,  Sally Liu

IPC分类号： G01R31/02 ,  G06F11/22 ,  H01L23/58

CPC分类号： G01R31/2846 ,  G01R31/27 ,  G01R31/2884 ,  Y10T29/49002

摘要： Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures.

摘要翻译： 提供了一种去嵌入的方法。 该方法包括形成具有嵌入其中的被测器件的测试结构，测试结构具有将测试器件耦合的左垫和右焊盘，被测器件分为测试结构和左半结构和右半结构， 每个都具有固有的传输参数的左，右半结构; 形成多个虚拟测试结构，每个虚拟测试结构包括左垫和右垫; 测量测试结构和虚拟测试结构的传输参数; 并使用左半结构和左半结构的固有传输参数以及测试结构和虚拟测试结构的传输参数导出待测器件的固有传输参数。

公开(公告)号：US08275584B2

公开(公告)日：2012-09-25

申请号：US11638303

申请日：2006-12-12

申请人： Chung-Kai Lin ,  Cheng Hsiao ,  Sally Liu

发明人： Chung-Kai Lin ,  Cheng Hsiao ,  Sally Liu

IPC分类号： G06F7/60 ,  G06F17/18 ,  G06F17/50 ,  G01N37/00 ,  G01R31/14

CPC分类号： G01R31/318357 ,  G01R31/3008 ,  G01R31/318314

摘要： A method of developing a statistical model for integrated circuits includes providing a set of test patterns; collecting a set of intra-die data from the set of test patterns; collecting a set of inter-die data from the set of test patterns; generating a total variation sigma (sigma_total) from the set of intra-die data and the set of inter-die data; appointing one of a global variation sigma (sigma_global) and a local variation sigma (sigma_local) as a first sigma, and a remaining one as a second sigma; generating the first sigma from one of the set of intra-data and the set of inter-data; generating the second sigma by removing the first sigma from the sigma_total; generating a corner model for global variations based on sigma_global and the set of inter-die data; and generating a corner model for local variations based on sigma_local and the set of intra-die data.

摘要翻译： 开发用于集成电路的统计模型的方法包括提供一组测试图案; 从所述一组测试图案中收集一组模内数据; 从所述一组测试图案中收集一组晶片间数据; 从所述管芯内数据集合和所述管芯间数据集合产生总变化Σ（sigma_total）; 任命一个全球变异西格玛（sigma_global）和一个局部变异西格玛（sigma_local）作为第一个西格玛，剩下的一个作为第二西格玛; 从所述一组内部数据和所述一组数据中的一个生成所述第一西格玛; 通过从sigma_total去除第一个sigma来产生第二个sigma; 生成基于sigma_global和集合的管芯间数据的全局变化的角模型; 并且基于sigma_local和一组模内数据生成用于局部变化的角模型。

公开(公告)号：US20110265051A1

公开(公告)日：2011-10-27

申请号：US12766732

申请日：2010-04-23

申请人： Tzu-Jin Yeh ,  Kal-Wen Tan ,  Chewn-Pu Jou ,  Sally Liu ,  Fu-Lung Hsueh

发明人： Tzu-Jin Yeh ,  Kal-Wen Tan ,  Chewn-Pu Jou ,  Sally Liu ,  Fu-Lung Hsueh

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.

摘要翻译： 根据实施例，用于衬底噪声分析的方法包括使用基于第一处理器的系统，创建和模拟包括晶体管的多端子模型的电路原理图，然后基于电路原理图中所示的特性创建布局 和仿真结果的模拟。 多端子模型包括源极端子，栅极端子，漏极端子，主体端子和保护环端子。

公开(公告)号：US20110001504A1

公开(公告)日：2011-01-06

申请号：US12496946

申请日：2009-07-02

申请人： Shu-Ying Cho ,  Jiun-Kai Huang ,  Wen-Sheh Huang ,  Sally Liu

发明人： Shu-Ying Cho ,  Jiun-Kai Huang ,  Wen-Sheh Huang ,  Sally Liu

IPC分类号： G01R31/02 ,  H01S4/00 ,  H01L21/66 ,  G01R31/26

CPC分类号： G01R31/2846 ,  G01R31/27 ,  G01R31/2884 ,  Y10T29/49002

摘要： Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures.

摘要翻译： 提供了一种去嵌入的方法。 该方法包括形成具有嵌入其中的被测器件的测试结构，测试结构具有将测试器件耦合的左垫和右焊盘，被测器件分为测试结构和左半结构和右半结构， 每个都具有固有的传输参数的左，右半结构; 形成多个虚拟测试结构，每个虚拟测试结构包括左垫和右垫; 测量测试结构和虚拟测试结构的传输参数; 并使用左半结构和左半结构的固有传输参数以及测试结构和虚拟测试结构的传输参数来导出被测设备的固有传输参数。

公开(公告)号：US08627253B2

公开(公告)日：2014-01-07

申请号：US12766732

申请日：2010-04-23

申请人： Tzu-Jin Yeh ,  Kal-Wen Tan ,  Chewn-Pu Jou ,  Sally Liu ,  Fu-Lung Hsueh

发明人： Tzu-Jin Yeh ,  Kal-Wen Tan ,  Chewn-Pu Jou ,  Sally Liu ,  Fu-Lung Hsueh

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.

摘要翻译： 根据实施例，用于衬底噪声分析的方法包括使用基于第一处理器的系统，创建和模拟包括晶体管的多端子模型的电路原理图，然后基于电路原理图中所示的特性创建布局 和仿真结果的模拟。 多端子模型包括源极端子，栅极端子，漏极端子，主体端子和保护环端子。

公开(公告)号：US08373229B2

公开(公告)日：2013-02-12

申请号：US12871476

申请日：2010-08-30

申请人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Feng Yuan ,  Sally Liu

发明人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Feng Yuan ,  Sally Liu

IPC分类号： H01L27/02

CPC分类号： H01L27/1211 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/785

摘要： An integrated circuit device is disclosed. An exemplary integrated circuit device includes: a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over the base portion of the fin structure. The collector portion is a first doped region including a first type dopant, and is coupled with a first terminal for electrically biasing the collector portion. The emitter portion is a second doped region including the first type dopant, and is coupled with a second terminal for electrically biasing the emitter portion. The base portion is a third doped region including a second type dopant opposite the first type, and is coupled with a third terminal for electrically biasing the base portion. The gate structure is coupled with a fourth terminal for electrically biasing the gate structure, such that the gate structure controls a path of current through the base portion.

摘要翻译： 公开了一种集成电路器件。 示例性的集成电路器件包括：半导体衬底; 翅片结构，设置在所述半导体衬底上; 以及设置在所述翅片结构的基部上的栅极结构。 集电极部分是包括第一类型掺杂剂的第一掺杂区域，并且与用于电偏置集电极部分的第一端子耦合。 发射极部分是包括第一类型掺杂剂的第二掺杂区域，并且与用于电偏置发射极部分的第二端子耦合。 基极部分是包括与第一类型相反的第二类型掺杂物的第三掺杂区域，并且与用于电偏置基极部分的第三端子耦合。 栅极结构与用于电偏置栅极结构的第四端子耦合，使得栅极结构控制电流通过基极部分的路径。

公开(公告)号：US08324970B2

公开(公告)日：2012-12-04

申请号：US12894903

申请日：2010-09-30

申请人： Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Sally Liu

发明人： Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Sally Liu

IPC分类号： H03F3/04

CPC分类号： H03F3/19 ,  H01L29/78

摘要： A radio frequency amplifier circuit includes a substrate that is capable of receiving a substrate bias voltage. The source of a transistor is capable of receiving a source bias voltage. The drain of the transistor is capable of receiving a drain bias voltage. The gate of the transistor is located between the source and the drain. A radio frequency input signal is coupled to the gate. A substrate bias circuit provides the substrate bias voltage. The substrate bias voltage and the source bias voltage forward bias the first diode formed by the source and the substrate. The substrate bias voltage and the drain bias voltage reverse bias the second diode formed by the drain and the substrate.

摘要翻译： 射频放大器电路包括能够接收衬底偏置电压的衬底。 晶体管的源极能够接收源极偏置电压。 晶体管的漏极能够接收漏极偏置电压。 晶体管的栅极位于源极和漏极之间。 射频输入信号耦合到门。 衬底偏置电路提供衬底偏置电压。 衬底偏置电压和源极偏置电压正向偏置由源极和衬底形成的第一二极管。 衬底偏置电压和漏极偏置电压反向偏置由漏极和衬底形成的第二二极管。