公开(公告)号：US10037625B2

公开(公告)日：2018-07-31

申请号：US15266075

申请日：2016-09-15

Applicant: Intel Corporation

Inventor： Tomas G. Akenine-Moller ,  Carl J. Munkberg ,  Jon N. Hasselgren

IPC: G06T17/20 ,  G06T1/20

CPC classification number: G06T17/20 ,  G06T1/20 ,  G06T15/005 ,  G06T2210/52

Abstract: Briefly, in accordance with one or more embodiments, an architecture to load balance tessellation distribution apparatus comprises a memory to store one or more patches representing an object in an image, and a processor, coupled to the memory, to perform one or more tessellation operations on the one or more patches. The one or more tessellation operations including splitting one or more of the patches into one or more subpatches, and load balancing the one or more patches and the one or more subpatches among two or more geometry and setup fixed-function pipelines (GSPs).

公开(公告)号：US09761001B2

公开(公告)日：2017-09-12

申请号：US14575197

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Magnus Andersson ,  Jon N. Hasselgren ,  Carl J. Munkberg ,  Tomas Akenine-Moller

IPC: G06T7/00 ,  G06T11/40 ,  G06T13/20 ,  G06T15/04 ,  G06T15/60

CPC classification number: G06T7/215 ,  G06T11/40 ,  G06T13/20 ,  G06T15/04 ,  G06T15/60 ,  G06T2215/12

Abstract: A layered, filtered shadow mapping algorithm may be used for motion blurred shadows. The algorithm is divided into two passes, namely a shadow pass and a lighting pass. The shadow pass renders the scene using stochastic rasterization and generates a time-dependent shadow map augmented with per-sample motion vectors. The subsequent lighting pass renders the scene from the camera's point of view, and performs a shadow query for each sample seen from the camera.

公开(公告)号：US09659393B2

公开(公告)日：2017-05-23

申请号：US14047079

申请日：2013-10-07

Applicant: Intel Corporation

Inventor： Tomas G. Akenine-Moller ,  Carl J. Munkberg ,  Franz P. Clarberg

IPC: G06T3/00 ,  G06T11/40

CPC classification number: H02J7/007 ,  G01R19/0092 ,  G06T11/40 ,  H02J7/0052 ,  H02J7/0055 ,  H02J7/025 ,  H02J7/045

Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.

公开(公告)号：US20170011545A1

公开(公告)日：2017-01-12

申请号：US15261893

申请日：2016-09-10

Applicant: Intel Corporation

Inventor： Carl J. Munkberg ,  Karthik Vaidyanathan ,  Jon N. Hasselgren ,  Franz P. Clarberg ,  Tomas G. Akenine-Moller ,  Marco Salvi

IPC: G06T15/50 ,  H04N5/232 ,  G06T15/06

CPC classification number: G06T15/503 ,  G06T5/50 ,  G06T15/06 ,  G06T15/50 ,  G06T15/506 ,  G06T2200/21 ,  G06T2207/10052 ,  H04N5/23229

Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.

Abstract translation: 用于散焦模糊的实时光场重建可用于处理同时散焦和运动模糊的情况。 通过仔细地引入几个近似值，导出非常有效的剪切重建滤波器，即使在一些实施例中对于非常低数量的输入样本也可产生高质量图像。 该算法可以在时间上是稳健的，并且比以前的工作快两个数量级，使得它在一些实施例中适合于实时渲染和用于高质量渲染的后处理通行。

公开(公告)号：US09501864B2

公开(公告)日：2016-11-22

申请号：US14141523

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Tomas G. Akenine-Moller ,  Magnus Andersson ,  Jon N. Hasselgren ,  Carl J. Munkberg ,  Robert M. Toth

IPC: G06T15/40 ,  G06F3/14 ,  G09G5/393 ,  G06T9/00 ,  G06T15/00 ,  G09G5/39

CPC classification number: G06T15/405 ,  G06F3/14 ,  G06T9/00 ,  G06T15/005 ,  G09G5/39 ,  G09G5/393 ,  G09G2340/02 ,  G09G2360/122

Abstract: Because using the same number of bits per residual depth offset compression is not the best distribution of bits, the bits per residual may be distributed instead according to the content of the depths of a tile. For example, if the depth differences close to the Zmax are small, then fewer bits can be spent on residuals for the samples that are encoded relative to Zmax. Consequently, more bits can be spent on the residuals for the samples that are encoded relative to Zmin. As a result, more tiles succeed at compressing to the required number of bits.

Abstract translation: 因为每个残留深度偏移压缩使用相同数量的比特不是比特的最佳分布，所以根据瓦片的深度的内容可以分配每个残差的比特。 例如，如果接近Zmax的深度差小，则相对于Zmax编码的样本的残差可以花费更少的位。 因此，对于相对于Zmin编码的样本的残差，可以花费更多的比特。 结果，更多的瓦片成功地压缩到所需的位数。

公开(公告)号：US09390541B2

公开(公告)日：2016-07-12

申请号：US13858988

申请日：2013-04-09

Applicant: Intel Corporation

Inventor： Jon N. Hasselgren ,  Tomas G. Akenine-Moller ,  Carl J. Munkberg ,  Jim K. Nilsson ,  Robert M. Toth ,  Franz P. Clarberg

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: In accordance with some embodiments, a tile shader executes on a group of pixels prior to a pixel shader. The tile of pixels may be rectangular in some embodiments. The tile may be executed hierarchically, refining each tile into smaller subtiles until the pixel or sample level is reached. The tile shader program can be written to discard groups of pixels, thereby quickly removing areas of the bounding triangles that lie outside the shape being rasterized or quickly discarding groups of pixel shader executions that will not contribute to the final image.

Abstract translation: 根据一些实施例，瓦片着色器在像素着色器之前的一组像素上执行。 在一些实施例中，像素块可以是矩形的。 可以分层执行瓦片，将每个瓦片细化为较小的子屏幕，直到达到像素或样品级别。 可以将瓦片着色器程序写入丢弃像素组，从而快速移除位于正被光栅化的形状之外的边界三角形的区域，或快速丢弃不会对最终图像做出贡献的像素着色器执行组。

公开(公告)号：US09201487B2

公开(公告)日：2015-12-01

申请号：US13784950

申请日：2013-03-05

Applicant: Intel Corporation

Inventor： Tomas G. Akenine-Moller ,  Bjorn Johnsson ,  Magnus Andersson ,  Jim K. Nilsson ,  Robert M. Toth ,  Carl J. Munkberg ,  Jon N. Hasselgren

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/24

Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.

Abstract translation: 根据一些实施例，可以利用使用加盖帧时间的知识来降低功耗。 通常，加盖帧时间是在图形处理中应用电力进行渲染的预分配时间量。 通常，帧时间涉及在下一帧时间内仅施加空闲功率的功率和一些停机时间。 通过更好地利用该停机时间，在一些实施例中可以实现功耗降低。

公开(公告)号：US20190130634A1

公开(公告)日：2019-05-02

申请号：US16233449

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Tomas G. Akenine-Moller ,  Jon N. Hasselgren ,  Carl J. Munkberg

IPC: G06T15/40 ,  G06T11/40

CPC classification number: G06T15/40 ,  G06T11/40

Abstract: In accordance with some embodiments, a zero coverage test may determine whether a primitive such as a triangle relies on lanes between rows or columns or lines of samples. If so, the primitive can be culled in a zero coverage culling test.

公开(公告)号：US09990758B2

公开(公告)日：2018-06-05

申请号：US14574992

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Per Ganestam ,  Tomas Akenine-Moller ,  Carl J. Munkberg

IPC: G06T15/00 ,  G06T17/00

CPC classification number: G06T15/005 ,  G06T17/005 ,  G06T2210/12

Abstract: A system rapidly builds bounding volume hierarchies for ray tracing using both the CPU cores and an integrated graphics processor. The hierarchy is built directly into shared memory (between the CPU and GPU). The method starts by sorting the triangles along a space-filling curve, and then quickly sets up a number of mini-trees with a small number of triangles in them, which includes computing the bounding boxes of the mini-trees. This makes it possible to build the mini-trees using a surface-area heuristic in parallel on the graphics processor, while at the same time, the trees above the mini-trees are built in a top-down fashion using the CPU cores.

公开(公告)号：US20180075573A1

公开(公告)日：2018-03-15

申请号：US15260570

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Robert M. Toth ,  Carl J. Munkberg ,  Jon N. Hasselgren

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/005 ,  G06T2210/08

Abstract: Methods and apparatus relating to techniques for provision of minimum or maximum and bitwise logic AND or logic OR based coarse stencil tests are described. In an embodiment, metadata (corresponding to a plurality of pixels) is stored in memory. One or more operations are performed on the metadata to generate a stencil result. The one or more operations comprise a bitwise intersection operation or a bitwise union operation and/or a minimum operation or maximum operation. Other embodiments are also disclosed and claimed.