公开(公告)号：US20210049285A1

公开(公告)日：2021-02-18

申请号：US17083149

申请日：2020-10-28

Applicant: Intel Corporation

Inventor： Sundar VEDANTHAM ,  Bin LIN ,  Pravin PATHAK ,  Ximing CHEN ,  Chris MACNAMARA

IPC: G06F21/60 ,  G06F16/27

Abstract: Examples described herein relate to a manner of provide a time of life of data. In some examples, data and control parameters are received from a data source. The data can be encrypted and stored. In addition, at least a portion of the control parameters can be stored into a distributed ledger. In some examples, the portion of the control parameters include an indicator of expiration time of the data. In some examples, a data header for the data is generated, where the data header includes an indication that the data is subject to a limited life span and a data identifier. The data header can be accessed with a request to access the encrypted data. In some examples, a request to determine if the data is valid and accessible is provided to a node of the distributed ledger and an indication of whether the data is valid and accessible is received from a node in the distributed ledger.

公开(公告)号：US20200374310A1

公开(公告)日：2020-11-26

申请号：US16990684

申请日：2020-08-11

Applicant: Intel Corporation

Inventor： Amruta MISRA ,  John J. BROWNE ,  Chris MACNAMARA

IPC: H04L29/06

Abstract: Examples described herein relate to a computing system that alters a frequency of operation of a peripheral device interface between a network interface card and a processor based on detection of a traffic violation. In some examples, a frequency of operation of a peripheral device interface is reduced based on detection of a traffic violation. In some examples, IP packet fragments can include one or more of: IP packet fragments that are incomplete packets, IP packet fragment that are too small, IP packet fragments that result in excessive packets, or IP packet fragmentation buffer being full. In some examples, detecting a traffic violation is based on detection of IP packet fragments at one or more of: a network appliance, the network interface card, uncore, system agent, operating system, application, or a computing platform. In some examples, the peripheral device interface includes one or more of: a system agent, an uncore, a bus, a device interface, and a cache. In some examples, the peripheral device interface is part of a system on a chip (SoC) and the SoC also includes one or more of: a core, system agent, or uncore.

公开(公告)号：US20200287821A1

公开(公告)日：2020-09-10

申请号：US16755554

申请日：2016-08-05

Applicant: Intel Corporation

Inventor： Damien POWER ,  Chris MACNAMARA ,  Marco VARLESE

IPC: H04L12/725 ,  H04L12/24 ,  H04L12/46 ,  H04L29/08 ,  H04L29/12 ,  H04L29/06

Abstract: A Service Routing Agent and methods are disclosed that classify and route data service requests. One embodiment includes a control circuit and at least one orchestrator, processor, and service handler circuit. The control circuit performs a process to: receive a configuration of at least one service handler circuit, initialize a list of service handler circuits and associated applications, program the at least one processor to listen for data service requests associated with the application, receive a data service request, and determine whether a service handler circuit associated with the application has been activated; when the service handler circuit has been activated, forwards the data service request to the service handler circuit, and when the service handler circuit has not been activated, request that the service handler circuit be activated, and then forwards the data service request to the service handler circuit. The Service Routing Agent reports updated traffic statistics.

公开(公告)号：US20200225724A1

公开(公告)日：2020-07-16

申请号：US16833008

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Chris MACNAMARA ,  John J. BROWNE ,  Tomasz KANTECKI ,  David HUNT ,  Anatoly BURAKOV ,  Srihari MAKINENI ,  Nikhil GUPTA ,  Ankush VARMA ,  Dorit SHAPIRA ,  Vasudevan SRINIVASAN ,  Bryan T. BUTTERS ,  Shrikant M. SHAH

IPC: G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F1/20

Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

公开(公告)号：US20190384348A1

公开(公告)日：2019-12-19

申请号：US16480830

申请日：2017-02-24

Applicant: INTEL CORPORATION

Inventor： Vasudevan SRINIVASAN ,  Krishnakanth V. SISTLA ,  Corey D. GOUGH ,  Ian M. STEINER ,  Nikhil GUPTA ,  Vivek GARG ,  Ankush VARMA ,  Sujal A. VORA ,  David P. LERNER ,  Joseph M. SULLIVAN ,  Nagasubramanian GURUMOORTHY ,  William J. BOWHILL ,  Venkatesh RAMAMURTHY ,  Chris MACNAMARA ,  John J. BROWNE ,  Ripan DAS

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20190044873A1

公开(公告)日：2019-02-07

申请号：US16023560

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： John BROWNE ,  Chris MACNAMARA ,  Tomasz KANTECKI ,  Parthasarathy SARANGAM

IPC: H04L12/823 ,  H04L29/06 ,  H04L12/851 ,  H04L12/741 ,  H04L12/813

Abstract: Examples may include an apparatus having processing logic to receive a packet, to classify the packet based at least in part on a header of the packet, to apply one or more serial packet filter rules to the packet, and when parallel packet filter rules are selected to apply one or more parallel packet filter rules to the packet, wherein application of the serial packet filter rules is performed in parallel with application of the parallel packet filter rules.