公开(公告)号：US20230290851A1

公开(公告)日：2023-09-14

申请号：US17693156

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  YenTing CHIU ,  Tahir GHANI

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having additive gate structures are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric, and an intervening conductive seed layer between the P-type conductive layer and the first gate dielectric. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the N-type conductive layer and the second gate dielectric. The P-type gate stack is in contact with the N-type gate stack.

公开(公告)号：US20230290778A1

公开(公告)日：2023-09-14

申请号：US17694266

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  YenTing CHIU ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/775 ,  H01L29/78391 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/66742

Abstract: Gate-all-around integrated circuit structures having dual metal gates and gate dielectrics with a single polarity dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having a mid-gap conductive layer over a second gate dielectric including the high-k dielectric layer and the dipole material layer.

公开(公告)号：US20220416039A1

公开(公告)日：2022-12-29

申请号：US17357711

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  David J. TOWNER ,  Orb ACTON ,  Jitendra Kumar JHA ,  YenTing CHIU ,  Mohit K. HARAN ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L29/49

Abstract: An integrated circuit structure comprises a first and second vertical arrangement of horizontal nanowires in a PMOS region and in an NMOS region. A first gate stack having a P-type conductive layer surrounds the first vertical arrangement of horizontal nanowires. A second gate stack surrounds the second vertical arrangement of horizontal nanowires. In one embodiment, the second gate stack has an N-type conductive layer, the P-type conductive layer is over the second gate stack, and an N-type conductive fill is between N-type conductive layer and the P-type conductive layer to provide same polarity metal filled gates. In another embodiment, the second gate stack has an N-type conductive layer comprising Titanium (Ti) and “Nitrogen (N) having a low saturation thickness of 3-3.5 nm surrounding the nanowires, and the N-type conductive layer is covered by the P-type conductive layer.

公开(公告)号：US20220093598A1

公开(公告)日：2022-03-24

申请号：US17031832

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  Omair SAADAT ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.

公开(公告)号：US20190305102A1

公开(公告)日：2019-10-03

申请号：US15943567

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Ying PANG

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/51 ,  H01L21/28

Abstract: A PMOS gate structure is described. The PMOS gate structure includes a trench, a high-k metal layer on a bottom and on sidewalls of the trench and a flourine free tungsten layer on the surface of the high-k metal. The PMOS gate structure also includes a metal layer in a space in the n-type work function metal.