公开(公告)号：US20190044638A1

公开(公告)日：2019-02-07

申请号：US15980442

申请日：2018-05-15

Applicant: Intel Corporation

Inventor： Huimin Chen ,  David Harriman ,  Yong Yang

IPC: H04J3/16 ,  H04W52/02 ,  H04W72/04 ,  H04Q11/04

Abstract: An apparatus is provided, where the apparatus may include a first terminal and a second terminal to be coupled to a host via a first wire and a second wire, respectively; a rechargeable storage; and a data circuitry. The apparatus may, during a first time-period, receive power via the first wire and the second wire from the host, and store the power in the rechargeable storage, and during a second time-period, transmit data from the data circuitry to the host via the first wire and the second wire. The first and second time-periods may be non-overlapping time periods. The apparatus is to refrain from transmitting any data to, or receiving any data from, the host during the first time period.

公开(公告)号：US09860173B2

公开(公告)日：2018-01-02

申请号：US14145376

申请日：2013-12-31

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David M. Lee

IPC: G06F15/16 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  G06F5/06 ,  H04L12/835

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.

公开(公告)号：US09836424B2

公开(公告)日：2017-12-05

申请号：US14144309

申请日：2013-12-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F15/16 ,  G06F13/40 ,  A47K7/02 ,  G06F13/42

CPC classification number: G06F13/4068 ,  A47K7/028 ,  G06F13/4273 ,  G06F2213/0026

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US20150078401A9

公开(公告)日：2015-03-19

申请号：US14144400

申请日：2013-12-30

Applicant: Intel Corporation

Inventor： David Harriman

IPC: H04L29/06

CPC classification number: G06F13/4282 ,  G06F11/0745 ,  G06F13/4022 ,  H04L29/0653 ,  H04L69/22

Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type.