公开(公告)号：US10158585B2

公开(公告)日：2018-12-18

申请号：US13773255

申请日：2013-02-21

Applicant: INTEL CORPORATION

Inventor： Eliezer Tamir ,  Jesse C. Brandeburg ,  Anil Vasudevan

IPC: H04L12/861 ,  G06F9/48 ,  G06F9/52 ,  G06F9/32 ,  H04L12/879 ,  G06F9/448

Abstract: Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

公开(公告)号：US10127177B2

公开(公告)日：2018-11-13

申请号：US15645583

申请日：2017-07-10

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Eliel Louzoun

IPC: G06F13/00 ,  G06F13/40 ,  G06F9/50 ,  G06F13/24

Abstract: The present disclosure is directed to a unified device interface for a multi-bus system. In at least one embodiment, a system may comprise more than one data bus. Each data bus may be to convey data between an operating system (OS) and at least one device in the system, wherein a plurality of driver instances may facilitate interaction between the OS and a device via one or more of the data buses. In one embodiment, a main driver instance may be determined from the plurality of driver instances to present the device to the OS and coordinate operation of other driver instances. The other driver instances may map addresses in the memory of processing entities corresponding to each of the data buses and report these mappings to the main driver instance. Alternatively, a supervisory driver may be loaded to present the device and to control operation of the driver instances.

公开(公告)号：US20180191838A1

公开(公告)日：2018-07-05

申请号：US15396441

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Ben-Zion Friedman ,  Eliezer Tamir ,  John J. Browne ,  Stephen Thomas Palermo

IPC: H04L29/08 ,  H04L12/24 ,  H04L12/741 ,  H04L12/801 ,  H04L12/46 ,  H04L12/14

CPC classification number: H04L67/148 ,  H04L12/1403 ,  H04L12/1407 ,  H04L12/403 ,  H04L12/4641 ,  H04L41/0806 ,  H04L41/0813 ,  H04L41/084 ,  H04L41/0846 ,  H04L41/5003 ,  H04L47/125 ,  H04L67/38 ,  H04M15/66 ,  H04W4/24

Abstract: There is disclosed in an example, a computer-implemented method of providing network function virtualization orchestration (NFVO), including: determining that a first virtual network function (VNF) instance, providing a virtual service appliance on a virtual network, is to be migrated; provisioning a second VNF instance of the virtual service appliance; cloning configuration data from the first VNF to the second VNF; starting the second VNF without copying traffic data; and halting the first VNF. There is also disclosed an apparatus for performing the method, and a computer-readable medium having instructions for performing the method.

公开(公告)号：US09661007B2

公开(公告)日：2017-05-23

申请号：US14661311

申请日：2015-03-18

Applicant: Intel Corporation

Inventor： Iosif Gasparakis ,  Scott P. Dubal ,  Patrick Connor ,  Kapil Sood ,  Eliezer Tamir

IPC: H04L29/06 ,  G06F21/60 ,  G06F21/85 ,  H04L9/32

CPC classification number: H04L63/1416 ,  G06F21/60 ,  G06F21/85 ,  G06F2213/3808 ,  H04L9/32 ,  H04L63/0428

Abstract: Network interface devices with remote storage control. In some embodiments, a network interface device may include receiver circuitry and remote storage device control circuitry. The remote storage device control circuitry may be coupled to the receiver circuitry and may share a physical support with the receiver circuitry. The remote storage device control circuitry may be configured to control writing of data from the receiver circuitry to a remote storage device that does not share a physical support with the remote storage device control circuitry.

公开(公告)号：US09311110B2

公开(公告)日：2016-04-12

申请号：US13936964

申请日：2013-07-08

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Prafulla Deuskar ,  Phil C. Cayton

IPC: G06F9/44 ,  H04L29/08 ,  G06F3/06

CPC classification number: G06F9/4416 ,  G06F3/0688 ,  G06F9/4401 ,  H04L67/34

Abstract: Examples are disclosed for remotely initializing or booting a client or host device. In some examples, a network (NW) input/output (I/O) device coupled to a host device connects to a remote server via a NW communication link. For these examples, modules of the network I/O device establishes a control path to a non-volatile memory express (NVMe) controller maintained at the remote server using a remote direct memory access (RDMA) protocol. Properties of a storage device controlled by the NVMe controller have an RDMA service tag (STag) to indicate accessible allocated portions of the storage device. A system basic I/O system (BIOS) is capable of using the RDMA STag to access the storage device and load an operating system (OS) kernel. Also, one or more device drivers can remotely boot the host device using the RDMA STag.

Abstract translation: 公开了用于远程初始化或引导客户端或主机设备的示例。 在一些示例中，耦合到主机设备的网络（NW）输入/输出（I / O）设备经由NW通信链路连接到远程服务器。 对于这些示例，网络I / O设备的模块使用远程直接存储器访问（RDMA）协议建立到在远程服务器上维护的非易失性存储器快速（NVMe）控制器的控制路径。 由NVMe控制器控制的存储设备的属性具有RDMA服务标签（STag）以指示存储设备的可访问分配部分。 系统基本I / O系统（BIOS）能够使用RDMA STag访问存储设备并加载操作系统（OS）内核。 此外，一个或多个设备驱动程序可以使用RDMA STag远程引导主机设备。

公开(公告)号：US09256441B2

公开(公告)日：2016-02-09

申请号：US13659479

申请日：2012-10-24

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Boris Kleiman ,  Ben-Zion Friedman ,  Eliel Louzoun

IPC: H04L12/54 ,  G06F9/44

CPC classification number: G06F9/4415

Abstract: Generally, this disclosure provides systems and methods for providing forward compatibility between a driver module and one or more present or future versions of a network interface. The system may include a network interface configured to transfer data between a host system and a network; and a programmable circuit module associated with the network interface, the programmable circuit module configured to provide compatibility between the network interface and a driver module associated with the host system, wherein the driver module includes a first set of capabilities and the network interface includes a second set of capabilities.

Abstract translation: 通常，本公开提供用于提供驱动器模块与网络接口的一个或多个当前版本或未来版本之间的前向兼容性的系统和方法。 该系统可以包括被配置为在主机系统和网络之间传送数据的网络接口; 以及与所述网络接口相关联的可编程电路模块，所述可编程电路模块被配置为提供所述网络接口和与所述主机系统相关联的驱动器模块之间的兼容性，其中所述驱动器模块包括第一组能力，并且所述网络接口包括第二 一套能力。

公开(公告)号：US20140223026A1

公开(公告)日：2014-08-07

申请号：US13993525

申请日：2012-01-10

Applicant: INTEL CORPORATION

Inventor： Eliezer Tamir ,  Phil C. Cayton ,  Ben-Zion Friedman ,  Robert O. Sharp ,  Donald E. Wood ,  Vadim Makhervaks

IPC: H04L12/801

CPC classification number: H04L47/39 ,  H04L67/1097

Abstract: Generally, this disclosure relates to a method of flow control. The method may include determining a server load in response to a request from a client; selecting a type of credit based at least in part on server load; and sending a credit to the client based at least in part on server load, wherein server load corresponds to a utilization level of a server and wherein the credit corresponds to an amount of data that may be transferred between the server and the client and the credit is configured to decrease over time if the credit is unused by the client.

Abstract translation: 通常，本公开涉及一种流量控制的方法。 该方法可以包括响应于来自客户端的请求来确定服务器负载; 至少部分地基于服务器负载选择一种类型的信用; 并且至少部分地基于服务器负载向客户端发送信用，其中服务器负载对应于服务器的利用水平，并且其中信用对应于可在服务器和客户端之间传送的数据量以及信用 如果客户端没有使用信用额，则配置为随时间减少。

公开(公告)号：US11537419B2

公开(公告)日：2022-12-27

申请号：US15395884

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Krishnamurthy Jambur Sathyanarayana ,  Sean Harte ,  Thomas Long ,  Eliezer Tamir ,  Hari K. Tadepalli

IPC: G06F9/455 ,  H04L67/142

Abstract: Disclosed is a source host including a processor. The processor operates a virtual machine (VM) to communicate network traffic over a communication link. The processor also initiates migration of the VM to a destination host. The processor also suspends the VM during migration of the VM to the destination host. The source host also includes a live migration circuit coupled to the processor. The live migration circuit manages a session associated with the communication link while the VM is suspended during migration. The live migration circuit buffers changes to a session state and transfers the buffered session state changes to the destination host for replay after the VM is reactivated on the destination host. The live migration circuit keeps the sessions alive during migration to alleviate connection losses.

公开(公告)号：US10782978B2

公开(公告)日：2020-09-22

申请号：US16358154

申请日：2019-03-19

Applicant: INTEL CORPORATION

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: G06F9/32 ,  G06F1/32 ,  G06F9/38 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/50 ,  G06F9/46

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

公开(公告)号：US10552207B2

公开(公告)日：2020-02-04

申请号：US15386990

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: G06F9/30 ,  G06F9/48 ,  G06F8/41 ,  G06F9/50

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.