公开(公告)号：US10474174B2

公开(公告)日：2019-11-12

申请号：US15479217

申请日：2017-04-04

Applicant: INTEL CORPORATION

Inventor： Taesik Na ,  Harish K. Krishnamurthy ,  Xiaosen Liu

IPC: H02M3/335 ,  G05F1/575

Abstract: An apparatus is provided which includes: a first set of devices which is digitally controlled by a first feedback loop that includes a first comparator; and a second set of devices which is controlled by an analog circuitry which is part of a second feedback loop that includes an amplifier, wherein the first set of devices is coupled in parallel to the second set of devices.

公开(公告)号：US20190064907A1

公开(公告)日：2019-02-28

申请号：US15682724

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Dileep J. Kurian ,  Ankit Gupta ,  Akhila M ,  Tanay Karnik ,  Vaibhav Vaidya ,  David Arditti Ilitzky ,  Christopher Schaef ,  Sriram Kabisthalam Muthukumar ,  Harish K. Krishnamurthy ,  Suhwan Kim

IPC: G06F1/32

Abstract: Systems, apparatuses and methods may provide for early pre-charge with respect to peak power events. Application performance may improve by pre-charging a supercap just prior to initiating a system wake up from a qualified system wake-source trigger. Additionally, the pre-charging of the supercap may be controlled by a time defined pre-charge period and may also be controlled by a predetermined threshold voltage.

公开(公告)号：US10185382B2

公开(公告)日：2019-01-22

申请号：US15292067

申请日：2016-10-12

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Harish K. Krishnamurthy ,  Mohit Verma ,  Pradipta Patra ,  Uday Bhaskar Kadali

IPC: G06F1/00 ,  G06F1/32

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

公开(公告)号：US09490701B2

公开(公告)日：2016-11-08

申请号：US14325310

申请日：2014-07-07

Applicant: Intel Corporation

Inventor： George E. Matthew ,  Jessica Gullbrand ,  Krishnan Ravichandran ,  Willem M. Beltman ,  Karthik Sankaranarayanan ,  Sheldon Weng ,  Wayne L. Proefrock ,  Harish K. Krishnamurthy ,  Pavan Kumar

IPC: H02M3/157 ,  H02M3/158 ,  H02M3/00 ,  H02M1/44 ,  H02M3/156

CPC classification number: H02M3/158 ,  H02M1/44 ,  H02M3/005 ,  H02M3/157 ,  H02M3/1582 ,  H02M2003/1566

Abstract: Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了降低开关噪声和改善稳压器瞬态响应的方法和装置。 在一个实施例中，一个或多个脉冲被插入到电压调节器的输出波形中。 一个或多个脉冲将多个频率引入电压调节器的输出波形（例如，以减少声学噪声）。 在另一个实施例中，响应于输出电压与多个阈值中的至少一个的比较来修改电压调节器的输出电压。 多个阈值包括上触发点电压值和下触发点电压值。 还公开并要求保护其他实施例。