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公开(公告)号：US11411491B2
公开(公告)日：2022-08-09
申请号：US16642853
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
Abstract: Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.
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2.发明申请公开(公告)号：US20190190725A1
公开(公告)日：2019-06-20
申请号：US15846045
申请日：2017-12-18
Applicant: Intel Corporation
Inventor： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC: H04L9/32
CPC classification number: H04L9/3278
Abstract: An apparatus is provided which comprises: an array of physically unclonable function (PUF) devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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3.发明申请公开(公告)号：US20190094931A1
公开(公告)日：2019-03-28
申请号：US15718991
申请日：2017-09-28
Applicant: INTEL CORPORATION
Inventor： Khondker Z. Ahmed , Vivek K. De , Nachiket V. Desai , Suhwan Kim , Harish K. Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram R. Vangal
Abstract: Various embodiments of the invention may analyze previous patterns of harvested energy to predict future patterns of available harvested energy. This prediction may then be used to choose from among multiple methods of energy reduction techniques. The energy reduction techniques may include multiple versions of reducing or modifying instruction execution. Reduced instruction execution may include reducing the precision of various calculations.
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公开(公告)号：US20190006939A1
公开(公告)日：2019-01-03
申请号：US15638643
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Harish Krishnamurthy , Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.
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公开(公告)号：US20210203228A1
公开(公告)日：2021-07-01
申请号：US16727759
申请日：2019-12-26
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Krishnan Ravichandran , Harish Krishnamurthy , Vivek De
Abstract: A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.
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Patent Agency Ranking
公开(公告)号：US10530254B2
公开(公告)日：2020-01-07
申请号：US15632086
申请日：2017-06-23
Applicant: INTEL CORPORATION
Inventor： Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Harish Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.
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7.发明申请公开(公告)号：US20210103308A1
公开(公告)日：2021-04-08
申请号：US17100603
申请日：2020-11-20
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Harish Krishnamurthy , Krishnan Ravichandran , Vivek De , Scott Chiu , Claudia Patricia Barrera Gonzalez , Jing Han , Rajasekhara Madhusudan Narayana Bhatla
Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.
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8.发明授权公开(公告)号：US10958079B2
公开(公告)日：2021-03-23
申请号：US15939120
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Khondker Z. Ahmed , Vivek K. De , Nachiket V. Desai , Suhwan Kim , Harish K. Krishnamurthy , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav A. Vaidya , Sriram R. Vangal
Abstract: In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.
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公开(公告)号：US10474174B2
公开(公告)日：2019-11-12
申请号：US15479217
申请日：2017-04-04
Applicant: INTEL CORPORATION
Inventor： Taesik Na , Harish K. Krishnamurthy , Xiaosen Liu
Abstract: An apparatus is provided which includes: a first set of devices which is digitally controlled by a first feedback loop that includes a first comparator; and a second set of devices which is controlled by an analog circuitry which is part of a second feedback loop that includes an amplifier, wherein the first set of devices is coupled in parallel to the second set of devices.
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公开(公告)号：US10298117B2
公开(公告)日：2019-05-21
申请号：US15638643
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Harish Krishnamurthy , Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.
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